Previous Page  10 / 76 Next Page
Show Menu
Previous Page 10 / 76 Next Page
Page Background


Chip Scale Review January • February • 2017


Table 1

shows the total numbers of units

the panel and the wafer can produce per

each package size. As seen in

Figure 1


one single-batch processing for a panel

can produce almost 3 times as many units

as for a wafer, from which one can make

a natural guess of cost saving. How much

exact savings can be achieved using the

panel over the wafer is still in discussion [1].

Approaches for panel-level fan-out


Panel-level fan-out manufacturing can

be categorized in two different types.

One uses the current infrastructure of

substrate manufacturing, which is based

on a printed circuit board (PCB) approach.

This approach involves adding extra

equipment such as pick-and-place, panel

mold tools, grinder, and others. The

second type is a thin-film approach [2, 3].

It involves modifying wafer processing

tools to accommodate rectangular panels

rather than circular wafers. For example,

the manufacturer would define new tool

configurations for lithography, sputtering,

plating, imaging, and etching equipment for

rectangular panels [4]. One advantage of

the former approach is that it makes use of

a currently installed line, which minimizes

the capital investment. However, it has

process technology limitations for meeting

fine-pitch and feature requirements. The

second type has an advantage of having

wafer processing equivalent accuracy and

technology, but its disadvantage is the capex

investment and technology immaturity of

applying wafer (circle) processing to panel

(rectangular) processing. Both approaches

have common challenges, which can

result in yield loss during the various

manufacturing processes.

Despite the complexities mentioned,

there is a simple comparison of panel

versus wafer capacity analysis as shown


Table 2

. As the table shows, panel-

based solutions could produce nearly

three times the number of package units,

making a compelling case for panel-based

solutions. To meet the demand scenario

shown in

Table 2

, a capex investment of

~$200M will be needed for panel fan-out

equipment, while a capex investment of

~$400M will be needed for the capacity

of WLFO. The market price for a 7x7mm

package is conservatively

around 20+ cents, which, in

turn, results in the revenue

of $280M. Hence, there is

potential opportunity to make a

profitable return on investment

in a short time period.

It should be mentioned

that the process risk factors

are not considered in this

calculation. However panel-

level processing can possibly

build upon the infrastructure

developed during the last

decade for fan-out technology.

TSMC’s InFO, for example,

demonstrates a monumental

milestone for a new paradigm

of packaging technology in

terms of getting rid of substrate,

proximate system integration

of chip-to-packaging and “real”

fab-like backend manufacturing



From the cost standpoint,

panel-level fan-out (PLFO)

i s a v i ab l e concep t and

feasible. Even though it is currently in the

development stage, thin-film based PLFO

will probably enter volume production

during the next few years. Due to technical

challenges, it may be initially applicable

to products requiring only a single

redistribution layer. Once the equipment

infrastructure matures, panel-level fan-out

processing may be extended to applications

that require multi-layer redistribution.

In the foreseeable future, WLFO will be

extended to multi-die applications using

finer line and space capability to support

further integration of packaging. We are

seeing the embryonic era of the fan-out

market, which can hopefully be another

driving force in leading mobile, as well as

automotive and computing markets.


1. C. Pa l esko , A. Lu j an , “Cos t

comparison of fan-out wafer-level

packaging to fan-out panel-based

packaging,” IMAPS 2016.

2. T. Braun, et al., “Opportunities and

challenges for fan-out panel-level

package,” SEMICONTaiwan 2015.

3. “The movement to large-area

packaging: opportunities and

options,” TechSearch International

2015; asp?section_id=36&doc_id=1330300

4. S. Kumar, A. Pizzagalli, “Status

o f p a n e l - l e v e l p a c k a g i n g

m a n u f a c t u r i n g , ” Y o l e

Dévelopment, 2015.


Choon Lee received his MS and PhD

degrees from Case Western Reserve

U. and is Global CTO for Advanced

Packaging at Lam Research; email

Thomas Bondur received his BS

degree in Business from the State U. of

New York and is Corporate VP of the

Advanced Packaging Business Group at

Lam Research.

Manish Ranjan received his MBA

from The Wharton School of Business

in Philadelphia, PA and is the Managing

Director of the Advanced Packaging

Business Unit at Lam Research.

Table 1:

Comparison of the total number of units that can be

processed by panel-level processing or wafer-level processing.

Figure 1:

Area comparison of a wafer vs. a panel.

Table 2:

Needed capacity of panel vs. wafer processing assuming

1.4Bunits/year for a 7x7mm package.