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Chip Scale Review January • February • 2017




January • February 2017

Volume 21, Number 1

The cover shows two different optoelectronic

interconnection methods developed to enable

photon and electron conversion at the level of

the microelectronic (logic) chip. Parallelized

optical fibers (front) and lithographically-defined

compliant polymer waveguides (behind) carry

data in optical form to/from the IC. The flip-chip

bumps on each die form the electrical connections

to the package substrate. As optoelectronic

conversion moves closer to the chip, improved

data transfer speeds, bandwidth and power

efficiencies are expected.

Cover image courtesy of IBM Corporation

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Technology Trends 7 Technology and economic considerations for panel-level fan-out packaging Choon Lee, Tom Bondur, Manish Ranjan Lam Research Patents 68 The benefits of cross-licensing for IC packaging By Kevin Roe Intellectual Property Attorney Phil Marcoux PPM Associates Guest Editorial 11 Data center O/Is could pave the way for the photonic-in-package era Eric Mounier, Thibault Buisson Yole Développement 66 Package integration driving RF test complexity and requirements Judy Davies Advantest The future of packaging with silicon photonics Deborah Patterson Patterson Group, LLC Isabel De Sousa, Louis-Marie Achard IBM Canada, Ltd. 14 Electrodeposition of Ø50 x 50µm Cu pillars for 3D stacking applications Zaid El-Mekki, Harold Philipsen, Mia Honore, Aleksandar Radisic, John Slabbekoorn, Herbert Struyf imec Marco Arnold, Alexander Fluegel, Dieter Mayer BASF SE Iris Shu-Ya Chang BASF Taiwan, Ltd. 28