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Chip Scale Review January • February • 2017


Electrodeposition of Ø50 × 50µm Cu pillars for 3D

stacking applications

This article was originally published in the IWLPC 2016 Conference Proceedings. It has been modified for this publication.

n this work, we demonstrate defect-

free plating of Ø50 × 50µm Cu

pillars on 300mm wafers, for 3D

stacking applications. We also demonstrate

the capability to control and tune within-

wafer (WIW) and within-die (WID)

uniformity of Cu pillar heights to given

application requirements. Furthermore,

by adjusting the concentration of plating

additives, we are able to modify the shape

and morphology of electroplated Cu pillars.


Electrochemically deposited pillars/

bumps are an integral part of 3D technology

[1,2]. Electrodeposition offers the capability

to fabricate complex structures at high

throughput and lower cost than other

deposition techniques. However, it is not

immune to challenges such as tighter

specifications for within-wafer and within-die

pillar/bump height uniformity, or achieving

specific structure shape and morphology,

which present themselves with downscaling.

For example, within-die uniformity (or

coplanarity) is of special interest because of

the fact that variations in pillar height within

a die might have serious consequences on

post-plating processing steps such as die-to-

die and die-to-wafer stacking.

In order to meet the specifications for

successful application of pillars/bumps in 3D

technology, an electrochemist has a number

of means to do so. These could involve, for

example, substrate-surface pretreatments,

modifying bath composition, various mass

transport control methods, various current

deposition waveforms, controlling the bath

temperature, specific tool setup, etc.

A typical Cu plating bath for fabrication

of Cu interconnects for applications in

microelectronics industry could contain a

basic makeup with a source of Cu ions and

a supporting electrolyte, and a number of

organic additives. The additives are often

designated as suppressors, accelerators,

levelers, and grain refiners, according to

their role in the electrodeposition process.

Type, amount, ratio to other components,

and their interactions during the plating

process could have a profound influence

on the properties of the plated Cu. The

maximum temperature of the plating bath in

a typical production tool is limited to about

60˚C. This does not seem like much, but

the variation in temperature of only several

degrees could have a significant effect on

the quality of the deposit.

In this paper, we report on wafer-level

plating of Ø50 × 50µm Cu pillars. We

examine the role of the surface pretreatment,

bath composition, plating parameters, and

tool setup in controlling the within-wafer

(WIW) and within-die (WID) uniformity

of Cu-pillar heights. Plated Cu pillars are

characterized using optical microscopy

(OM), scanning electron microscopy (SEM),

focused ion beam (FIB), laser scanning

microscopy (LSM), and other physical/

chemical characterization techniques.

Based on the acquired measurements

and the observed trends, we optimize

the experimental parameters to match

application requirements.


All wafer-level plating experiments

were performed using an AMAT Raider

electroplating tool with segmented

anodes, enabling additional adjustment of

the deposition current distribution. Copper

plating chemistries from CUPUR® U

Series (BASF’s copper plating series

f o r wa f e r- l eve l pa ckag i ng (WLP )

applications) including Virgin makeup

solutions (VMS, basic aqueous Cu

bath with source of Cu ions, supporting

electrolyte, and inorganic components),

and all the additives, accelerator,

suppressor, and leveler, are provided by

BASF SE (Ludwigshafen, Germany).

Screening of useful concentration ranges

of various bath components under

different deposition conditions was

performed on a coupon-level in a lab-

bench plating tool at BASF laboratories,

and was used as a starting point in wafer-

level studies.

Cu pillars were plated on 300mm

wafers with cylindrical openings 50µm

in diameter and 60µm deep, as shown

schematically in

Figure 1

. In all of our

experiments, the 150nm Cu seed and the

30nm TiW barrier layer, fabricated using

physical vapor deposition (PVD), were

used as a substrate.

The Cu pillars are defined in a 60µm

thick positive tone I-line layer by

exposure on an Ultratech AP300 wafer

stepper. Prior to plating, the diameter

of the resist openings was measured

simultaneously across the whole wafer

using a Falcon 630 Plus tool (Camtek

Ltd), with critical dimensions allowed

to deviate ±2µm. The variations/non-

uniformity of the diameter of the openings

have direct impact on the wafer-level

height uniformity of the plated Cu pillars,

making this quality control step a must.


Figure 1:

Schematic representation of the substrate,

showing the dimensions of the opening in the

photoresist, and barrier/seed (TiW/Cu) layer thickness

(not drawn to scale).

By Zaid El-Mekki, Harold Philipsen, Mia Honore, Aleksandar Radisic, John Slabbekoorn,

Herbert Struyf


; and Marco Arnold, Alexander Fluegel, Dieter Mayer


; and Iris Shu-Ya Chang

[BASF Taiwan, Ltd.]