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Chip Scale Review January • February • 2017


Surface insulation resistance of no-clean flux residues

under various surface mount components

By Bruno Tolla, Denis Jean, Kyle Loomis, Yanrong Shi


o-clean fluxes present great

benefits for the electronic

assembly industry, but the

activity of the unwashed process residues

must be tightly controlled in order to

meet high reliability standards. The

pervasive miniaturization trends of the

industry, coupled with the intricacy of

the new component architectures, has

profoundly affected the nature and the

reactivity of the flux residues. A series of

customized surface insulation resistance

(SIR) experiments under various surface

mount components demonstrate the

dramatic impact of the partial activation

and restricted outgassing of the fluxes

on the reliability of the final assembly.

Mainstream no-clean pastes and liquid

fluxes, which are qualified under all

the standard SIR and ECM reliability

tests, present SIR values several decades

lower than the 100MΩ limit mandated

by IPC J-STD-004B when tested with

quad-flat no-leads (QFNs) packages.

Different surface mount components

(e.g., passive, quad flat package [QFP],

ball grid array [BGA]) can be more

or less forgiving depending on the

induced heat gradients and resistance to

outgassing. From this perspective, we

demonstrate how a thorough examination

of the interplay between assembly

architecture, processing conditions

and flux formulation is the necessary

condition for the design of reliable fluxes

mitigating the risks of in-field failures

of the final assembly. This study forms

the background for the proposal of

new reliability testing standards for the

electronic assembly industry.


The electronic assembly industry

is perpetually evolving to satisfy the

ever-increasing needs for performance,

efficiency, versatility, and system

integration in robust and cost-effective

packages. From the big data revolution

to energy efficiency problematics, from

consumer to industrial applications,

these driving forces result in growing

system complexities. From an assembly

p r oc e s s pe r s pe c t i ve , i n t e r conne c t

densities are constantly increasing,

while form factors, stand-off heights,

and component layouts at various

scales are always more challenging.

These trends, associated with the needs

for mobility and end-use in challenging

environments, greatly increase the

sensitivity of modern electronics to in-

field failures. Meanwhile, there has

been little progress in the definition

of reliability qualification protocols

for these assemblies. The certification

standards do not reflect the current

design trends and the industry as a

whole is calling for more predictive

t e s t s . Be c a u s e o f t h e c omp o n e n t

and architecture complexity, and the

great variety of assembly materials

and p r oce s s e s , i t i s o f pa r amoun t

importance to design model testing

vehicles and protocols allowing the

study of specific reliability failure

modes. This paper represents such an

attempt by focusing on the dramatic

influence of surface mount components

on reliability failures from assembly

materials (solder pastes and fluxes).

The design of testing boards involving

multiple component types in various

configurations allows a methodical

study of the interaction of materials,

components and assembly processes. It

also allows us to analyze the multiple

chemical mechanisms at play during

t he a s s emb l y p r oc e s s , wh i ch wi l l

ultimately drive the reliability of the

electronic device during its operating

l i f e . I t t he r e f o r e con t r i bu t e s t o a

fundamental understanding of the in-

field failure of complex electronic

architectures, which is a necessary

condition for the design and adequate

testing of robust products.


Th e e q u i pme n t a n d p r o c e d u r e s

u s e d d u r i n g o u r i n v e s t i g a t i o n s

are regrouped in this section. The

specifics of our testing methodology

( t emp e r a t u r e , v o l t a g e g r a d i e n t s ,

h um i d i t y l e v e l s , e x p o s u r e t i me ,

component characteristics) have a

critical influence on the outcome of

the test, as will be discussed in the

following section.

Temperature calibration study.

L o c a l t e m p e r a t u r e c o n d i t i o n s

e x p e r i e n c e d b y t h e a s s e m b l y

materials (flux and solder pastes)

were recorded by means of a Mole

thermal profiler, whose thermocouples

were placed in the interconnecting

area between a standard IPC-B-24

SIR board and conventional quad flat

packages (QFP208). The assemblies

we r e s ub j e c t ed t o va r i ou s r e f l ow

profiles using a Speedline Electrovert

OmniExcel 7-zone oven.

Su r f a c e i n s u l a t i on r e s i s t an c e

( S I R ) .

A l l t e s t s w e r e e x e c u t e d

according to the joint industry standard

IPC J-STD-004B, under test method

IPC-TM-650 §, involving SIR

monitoring over a period of 7 days of

an IPC-B-24 board exposed to a moist

environment (40ºC, 90% RH) under a

constant bias of 12.5VDC. This board

is made of bare copper on an FR-4

epoxy laminate. It consists of four

comb patterns formed by interdigitated

Cu traces (width: 0.4mm, spacing:

0.5mm). A Vitronics Delta3 industrial-

scale wave soldering machine was

used for the application of pattern-up/

pattern-down soldering profiles. All

other flux preconditioning and reflow

p r o t oco l s we r e c a r r i ed - ou t i n t he

7-zone oven described above.

S I R a s s e s s me n t s u n d e r BGA


The standard IPC-B-24

board was customized by replacing

the interdigitated connector pattern