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Chip Scale Review January • February • 2017


Advances and applications of gold electroplating for

wafer-level packaging

By Therese Souza, Lynne Michaelson

[Technic Inc.]

This article was originally published in the IWLPC 2016 Conference Proceedings. It has been modified for this publication.

ver the years, thick gold

films have been applied to

wafers to utilize gold’s unique

electrical and mechanical properties. This

paper will review the current state-of-the-

art application of gold plating onto wafers,

substrates, and wafer-level packages by

electroplating. We will also examine new

developments in formulations of cyanide

(CN) free chemistries that offer improved

ease of use, neutral pH, higher stability, and

are free of heavy metal additives.

Gold plating applications

Gold plating is used in many industries to

take advantage of gold’s electrical, thermal,

and mechanical properties. For example, in

the semiconductor industry, gold plating is

used for a variety of bonding applications due

to gold’s corrosion resistance and mechanical

properties. In the microelectromechanical

sensor (MEMS) industry, gold compression

bonding is used where low temperatures

(<200ºC) are required. Tall gold pillars are

plated on liquid crystal display (LCD) drivers

and bonded to printed wiring boards (PWBs)

using thermal compression bonding. In flip-

chip and chip-scale packaging applications,

the under bump metal (UBM) stack has

gold as a final surface finish. In addition

to bonding applications, the electrical and

thermal properties of gold make it useful for

backside and via plating on power amplifiers

that are used in cell phone applications. The

majority of these semiconductor applications

require soft, pure gold. This paper will

discuss the development of a cyanide-free,

acidic gold plating bath that is compatible

with photoresist and is more stable than the

existing commercially available alkaline

cyanide-free plating baths.

Electroplating bath compatibility

Compatibility of photoresist with the

gold electroplating bath is one of the most

important issues when discussing gold

electroplating in the semiconductor industry.

The cyanide-based baths can be formulated

to be alkaline (pH>8.5), acidic buffered baths

(pH between 1.8–6), and neutral, buffered

baths (pH between 6 and 8.5) [1]. Even over a

wide pH range, these baths attack photoresist

because free cyanide is produced [1]. Non-

cyanide plating baths can be formulated to

be compatible with photoresists they are not,

however, as stable as the cyanide-based plating


Table 1

compares the stability constant

of the gold cyanide complex to the most

commonly used non-cyanide gold complex:

gold sulfite. The gold sulfite complex is much

less stable than the cyanide complex when

comparing their stability constants, gold sulfite



) vs. gold cyanide (K=10


) [1]. In

addition, the gold sulfite

complex is most stable at

an alkaline pH. Because

most photoresists tend

to be soluble in alkaline

solutions, sulfite gold

plating baths are generally

formulated to have a pH

between 8 and 10 in order

to minimize the dissolution of the photoresist.

A neutral to acidic pH is most desirable for

resist compatibility; this condition, however, is

not as stable for the gold sulfite complex.

A combination of proprietary stabilizers

and heavy metal additives have been used to

formulate sulfite gold plating baths that have

decent stability while being compatible with

resists [2]. However, most of these plating

baths are still alkaline (pH of 8-10) and contain

hazardous heavy metal additives that start to

negate the health and safety benefits of the

sulfite gold plating bath versus the cyanide

gold plating bath.

In addition to better resist compatibility

and less health and safety issues, the sulfite

gold plating bath has a few other advantages

over the cyanide-based baths. Sulfite gold

plating baths are known to have better

throwing power than cyanide-based baths [3].

This benefit enables good step coverage and

uniform plating for semiconductor applications

requiring via and backside plating. In addition,

low stress, specifically compressive stress, is

required for many gold plating applications in

the semiconductor industry. The sulfite gold

bath can be formulated to have low stress [1].

Finally, pure gold deposits with lower surface

roughness and high electrical conductivity

are often required [2]. A properly formulated

sulfite gold plating bath can produce a gold

deposit that meets the above requirements [2].

Morrisey [4] developed a sulfite gold

bath stable to a pH of 4.5 using polyamines

and aromatic nitro compounds as additives.

Although this plating bath worked well

in small installations, there were some

consistency issues that prevented this bath from

being used in high-volume manufacturing.

Further study of Morrisey’s bath resulted in a

reformulation of this sulfite gold plating bath.

A proprietary stabilizer was discovered that

enables the bath to have excellent stability

and to be operated at an acidic pH. Successful

operation of this acid sulfite gold plating bath

across four different manufacturing toolsets,

as well as numerous wet benches and research

plating tools, demonstrates the versatility

of this chemistry. The following paper will

discuss the operation and performance of this

acid sulfite gold plating bath.

Electrolyte operation

In the semiconductor industry, it is critical

that the gold plating bath is compatible with

photoresist because many of the parts are

plated through a mask. As shown in



, resist dissolution typically occurs at an

alkaline pH of 10 or higher. In addition,

cyanide-based gold plating baths are not


Table 1:

Stability constants for selected gold complexes [1].