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Chip Scale Review January • February • 2017

[ChipScaleReview.com]

package, a ground plane corresponding

to an additional copper structure helps

to limit the die shift and provides

electromagnetic (EM) shielding as well

as more more rigidity to the package.

The supply chain used by Infineon

and NXP for FOWLP is different. Both

players have internally developed

their packaging platform – the eWLB

for Infineon and the RCP for NXP –

but only Infineon choose to keep the

manufacturing internally. Although

the eWLB process has been licensed

to other outsourced semiconductor

assembly and test (OSAT) players, the

packaging of radar chips is still made

by Infineon in Germany on 200mm (8-

inch) wafers. On the other hand, NXP

prefers to rely on NEPES, a South

Korean OSAT specialized in wafer-

level packaging and using 300mm (12-

inch) production lines. We calculated

that this choice to subcontract to a

300mm producer relies on a 20% lower

packaging cost.

FOWLP for consumer applications

FOWLP could find many potential

a p p l i c a t i o n s i n mo b i l e p h o n e s .

Applications such as baseband, power

management, RF transceivers, and

audio codec are all looking to this

platform for potential performances

and cost saving reasons.

The first FOWLP component we

observed in 2009 was an Infineon

baseband chip found in a LG feature

phone. Since that

time, we found

other components

u s i n g t h i s

technology. The

Samsung Galaxy

S 7 , wh i c h wa s

released in March

2016, contains an

audio codec chip

using a FOWLP.

This audio codec

i s p a r t i c u l a r l y

i n t e r e s t i n g

b e c a u s e i t i s

p r e s e n t o n l y

i n ve r s i on s o f

t h e S a m s u n g

Galaxy S7 and S7

Edg e f e a t u r i ng

t h e Qu a l c omm

S n a p d r a g o n

8 2 0 p r o c e s s o r,

which has been mostly observed in the

U.S. Therefore, as shown in

Figure 5

,

two players supply Samsung for the

audio codec in the Galaxy S7 and S7

Edge: Qualcomm with the WCD9335

in versions featuring the Qualcomm

Snapdragon 820, and Cirrus Logic with

the CS47L91 in versions using the

Samsung Exynos 8890 processor.

The audio codec supplied by Cirrus

is packaged with a traditional fan-in

WLP (FIWLP) compared to a FOWLP

for Qualcomm. In term of silicon usage,

the Qualcomm solution, which also uses

an additional A/V processor from DSP

Group, consumes 40% less silicon area

compared to the Cirrus solution.

The FOWLP technology used for the

Qualcomm audio codec is the eWLB,

licensed by Intel/Infineon to several

outsourced semiconductor assembly and

test suppliers (OSATS) including ASE,

NANIUM S.A., and STATS ChipPAC.

To show the real interest in going from

a FIWLP to a FOWLP, we calculated

the cost to produce the Qualcomm

actual chip and compared it to the cost it

could have been if it had been packaged

with a FIWLP. The fan-out area of the

Qualcomm chip is very low compared

to radar chips because the die represents

80% of the package area. The molding

area all around the die is then very

limited as shown in

Figure 6

.

In the case of a FIWLP, the die size is

then 100% of the package area. By using

the same wafer front-end process (CMOS

40nm), we calculated that an increase of

25% (from 80% to 100%) of the die size

drive to a die cost increase of 20%. On

the other hand, the cost of the packaging

is lower for FIWLP. We calculated that

FOWLP steps are close to 50% more

expensive compared to FIWLP. But

packaging cost is much less expensive

compared to CMOS front-end cost. For

our component manufactured with a

CMOS 40nm process, the packaging cost

represents less than 15% of the total cost.

So at the end, the FOWLP solution with

a 50% cost increase for the packaging

and a 20% cost decrease for the front-

end is 10% less expensive compared

to the FIWLP solution. Of course the

results would have been very different if

the technology node used for the CMOS

was larger and therefore less expensive.

In this case, the cost increase of the

FOWLP steps would have driven a higher

component cost.

Figure 3:

a) (left) Infineon RRN7745P; b) (right) NXP MR2001RVK.

Figure 4:

a) (top) Infineon eWLB cross section; b) (bottom) NXP RCP cross section.

K e y p l a y e r s f o r F O W L P i n

au t omo t i ve r ada r app l i ca t i ons a r e

Infineon with eWLB package and NXP

with its RCP. Both are integrated in

automotive 77GHz radar for advanced

driver assistance systems (ADAS).

Infineon, through the eWLB platform,

has been largely adopted by Bosch in

long-range radars (LLR) and mid-range

radars (MMR), and NXP is mainly

integrated in the Continental Industrial

Sensors’ long-range advanced radar

sensor (ARS).

The NXP chipset in Continental

radar consists of three components,

e a c h p a c k a g e d w i t h FOWLP : a

3 - c h a n n e l r e c e i v e r ( 7 7 GH z ) , a

2-channel transmitter (77GHz) and a

4-channel voltage control oscillator

(VCO) (38.5GHz). On the other hand,

Infineon’s chipset solution only uses

two components: the 38GHz VCO

being integrated with the transmitter

die. As shown in

Figure 3

, the Infineon

and NXP components share the same

6mm x 6mm package footprint; and die

areas for both solutions represent only

25% of the packages’ area.

Figure 4

highlights the package

structure with SEM pictures of cross

sections. Infineon and NXP dies have

almost the same thickness, but the

molding is not subjected to the grinding

process for the RCP package. Infineon

uses an extra step to thin the epoxy until

the silicon die and adds a protective

layer on the package. For the RCP