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Chip Scale Review January • February • 2017


Improving stepper throughput with feed-forward

metrology of die placement error

By Tom Swarbrick, Keith Best

[Rudolph Technologies, Inc.]

an-in wafer-level packages,

such as flip chips, arrange

I/O contacts over the surface

of the die. The number of contacts is

limited by the size of the die. Fan-

out packaging processes allow chip

manufacturers to increase the I/O

count by artificially extending the die

surface. In fan-out processes the die

are embedded in an epoxy molding

compound with more space between

die than on the original wafer. The

reconstituted substrate may mimic the

shape of a wafer, allowing subsequent

processing in equipment designed

t o h a nd l e wa f e r s , o r i t ma y b e a

larger rectangular panel, conferring

benefits from certain economies of

scale in subsequent processing. After

reconstituting the wafer/panel, the fan-

out process uses thin film techniques

to create redistribution layers that

extend beyond the edges of the die and

onto the adjacent molding compound.

Finally, solder balls on contact pads

atop the redistribution layer provide

r e l i a b l e c o n n e c t i o n s t o a ma t i n g

printed circuit board. The additional

s p a c i n g b e t we e n d i e e x t e n d s t h e

surface area available for contacts and

permits an arbitrarily large number of

contacts per die.

A m a j o r c h a l l e n g e i n f a n - o u t

processing lines is the inaccuracy of die

placement on the reconstituted wafer/

panel. Die placement error can occur

in the initial placement and during the

reconstitution process, and die can

also shift in subsequent processing

steps. Accurate information about the

location of the die is required to ensure

that the interconnects formed in the

redistribution layer connect with the

I/O contacts of the die. Manufacturers

have addressed die placement error

by using a photolithography system to

measure the position of each die and

realign each exposure, i.e., die-by-

die alignment. Although effective, the

alignment process is time consuming

and can amount to as much as two-

thirds of the overall exposure cycle.

Eliminating die-by-die alignment in the

exposure tool can dramatically increase

its throughput, with commensurate

reductions in the cost-of-ownership of

lithography systems.

Here we describe an experiment

de s i gned t o demon s t r a t e e ff i c a cy

o f f e ed - f o rwa r d me a s u r emen t s i n

a c h i e v i ng a c c u r a t e ov e r l a y i n a n

a d v a n c e d p a c k a g i n g l i t h o g r a p h y

t o o l ( J e t S t e p® S e r i e s , Ru d o l p h


Measurement capability

Lithography processes generally

require overlay accuracy of 25% of the

feature size (critical dimension, CD).

Redistribution layer (RDL) interconnect

features are currently in the 5 to 15

micrometer range, although, they are

expected to continue to shrink down to

the 2 micrometer range in the foreseeable

future. Inspection and metrology systems

use optical imagery and image analysis

techniques to detect feature locations

and measure distances between features


Figure 1

). To establish the accuracy of

this measurement tool we evaluated a

test pattern on a stepper reticle generated

by e l ec t r on beam l i t hog r aphy – a

technique capable of creating patterns

with nanometer scale accuracy, well

beyond the requirements of RDL overlay.

The reticle comprised several arrays of


Figure 1:

NSX® Series optical microscope image of

one of the cells in the array in

Figure 2


Figure 2:

One of several box-in-box and circle-in-circle arrays from the test reticle.