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Chip Scale Review January • February • 2017

[ChipScaleReview.com]

Package integration driving RF test

complexity and requirements

By Judy Davies

[Advantest]

igh-performance wireless

mobile products allow us to

perform myriad connected tasks

every day – from holding virtual

meetings to watching streaming content to

navigating through city traffic. All of these

products are connected through a variety of

wireless standards. These include Long Term

Evolution (LTE), LTE-Advanced and LTE-A

Pro smartphone standards, as well as LTE-M,

Wireless Local Area Network (WLAN),

Global Positioning System (GPS), ZigBee®

and Bluetooth®. This glut of standards creates

technological complexities, as these wireless

technologies – many of which are enabling the

Internet of Things (IoT) – have requirements

and performance criteria that differ depending

on the application in which they’re being used.

Devices built on the Third-Generation

(3G) and Fourth-Generation (4G) LTE

broadband standards, which cover most

current frequencies, are being fully tested

and characterized before they are packaged,

assembled and shipped. Testing these RF-

based system-on-chip (SoC) devices and RF

transceivers for these applications creates

unique challenges, as does test of analog

baseband transceivers, with their various types

of function blocks – transmit digital-to-analog

converters (DACs), receive analog-to-digital

converters (ADCs), audio DACs and audio

ADCs, to name a few.

Looming on the horizon is the new Fifth-

Generation (5G) standard. It promises to bring

new levels of speed and capacity, with lower

latency and greater flexibility than LTE, but its

new encoding technologies and chip structures

will require new production, packaging and

test technologies. In fact, the expected needs of

next-generation wireless networks are shaping

the next-generation of RF test equipment.

Another factor is the proliferation of

advanced packaging methodologies – e.g., fan-

out wafer-level packaging (FOWLP), multi-

chip packages (MCPs), through-silicon vias

(TSVs), embedded passives and actives, and

systems-in-package (SIPs), to name a few.

These packages – all of which are competing

for further dominance – are impacting how

the industry goes about wafer sort, final test,

packaging test, burn-in and other steps required

to go from basic wafer fab to end product.

Packaging integration essential

Practically speaking, in terms of packaging

for RF transceivers, as well as for RF chips

in general, every RF device still comprises

a large number of passive components, such

as capacitors and inductors, which allows it

to be useable as an end product. Packaging

integration is thus essential to turning an RF

piece of silicon into a device that can easily

talk to the antenna in the RF space. Three key

aspects come into play in this regard:

1. Embedded passive devices – essential

to making useful RF end products

based on RF chips – embedded passives

are a key element that outsourced

semiconductor and test suppliers

(OSATS) bring to the party.

2. Multiple standards – every mobile phone

today utilizes a variety of standards, so

implementing an RF set that can deal with

various standards is critical. These multi-

purpose devices switch mode depending

on the user’s location, increasing their

complexity and contributing to their test

challenges.

3. Multiple antennas – instead of a

single antenna, multiple antennas are

increasingly being employed within a

wireless product. This is essential to

ensuring that the device will work no

matter how it is held by the user.

Turning all of these components into a decent

RF package is an art. Ultimately, flexibility and

scalability of automated test equipment (ATE)

is a fundamental requirement in order to test

these devices thoroughly – this includes both

early die sort and final test once the peripherals

and passives are attached within the integrated

package. Test of advanced packages also

requires more standardized ways of connecting

everything together, but which approach will

dominate is still being determined.

Regardless of the package technique

employed, more rigorous functional test and

more robust compliance test are essential for

the end-product requirement – this is where

precision, capability and bandwidth of new

equipment come into play. Combining a tester-

per-pin architecture with massive parallelism is

one approach to ensuring the high performance

and high utilization chipmakers need to get

their products to market more quickly, and at a

lower test cost.

Learning from the past

A great deal of discussion is underway

regarding how packaging impacts the way test

cards are developed. There is a parallel here to

what happened 10-15 years ago with respect to

printed circuit boards (PCBs). Virtually every

electronics company in the world created its

own PCBs, put its own components onto the

board, and put them into the electronic products

that were purchased from store shelves.

Board test was big business back then. That

business has now changed and the chain has

consolidated into subcontract manufacturing

of PCB assemblies by a handful of very large

players, with a few small ones hanging on.

Similarly, a significant change is coming

with respect to package integration – there will

be more and more integration as well as more

into a single piece of silicon, creating smaller

and smaller PCBs – or, in some cases, no

board at all. As this industry shift continues to

play out, the line between chip and package is

blurring – particularly with more intelligence

being put into the package. There’s also

increasing competition for business between

PCB load and assembly houses and OSATS,

particularly with more complex integration

schemes. What customers will choose depends

on whether they need one-stop shopping, which

the OSATS say they can do, or if there is still a

board aspect involved for which they’d prefer

to tap the capabilities of the more traditional

PCB load/assembly providers.

Regardless of how this shakes out, we know

from these past shifts in the PCB space that

integration at the package level will take time

to shake out. And the complexity will grow

even more, increasing the pressure on the test

sector to deliver methodologies that will allow

H

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