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Chip Scale Review January • February • 2017

[ChipScaleReview.com]

Technology and economic considerations for

panel-level fan-out packaging

By Choon Lee, Tom Bondur, Manish Ranjan

[Lam Research]

he era of “More than Moore”

has extended to the packaging

world. Packaging plays a

critical role in improving

electrical and thermal performance and

power consumption. Recently developed

packaging technologies such as high-

density wafer-level fan-out (WLFO) have

gained increased attention as a way to meet

performance and form factor requirements

in the semiconductor market. To ensure

broad adoption for this packaging

technology, several foundry and outsourced

semiconductor assembly and test (OSAT)

companies are considering the use of larger

panel size substrates. This article will

discuss some of the cost motivation and

performance challenges associated with the

use of panel substrates for fan-out wafer-

level packaging.

Tod a y, p a c k a g i ng i s e n a b l i ng

advances in consumer electronics such as

smartphones by enabling more transistors

on a smaller area. For example, in the

iPhone 7, the Apple applications processor

has around 150% more transistors even

though the chip has increased by only 20%.

For reference, the chip has approximately

3.3 billion transistors in a chip with an area

of 125mm

2

.

This latest generation of applications

processors is manufactured using a

technology called “integrated fan-out,”

which is based on high-density WLFO.

Several key building blocks for this

packaging technology include multiple

redistribution layers and mega pillars to

support the package-on-package (PoP)

structure. Packaging innovations include

the use of mega pillars with 200µm

diameter and 200µm height instead of

a through-mold via (TMV) for a typical

PoP structure. Furthermore, the top-level

memory package height was reduced using

a side-by-side arrangement of LPDDR4

memories (instead of conventional

memory die stacking), and the impressive

introduction of 0.3mm ball pitch for the

first time in memory history. Lastly, this

technology introduction eliminated the use

of flip-chip substrates, thereby enabling a

reduction in overall package height. At the

2016 ICEP conference in Sapporo, Japan,

Google demonstrated the advantages

associated with the combination of

application processor and memory in a

planar layout to boost memory performance

and reduce power usage. It is evident

that the use of packaging technology for

enabling next-generation system-level

performance is gaining increased focus

from several top-tier semiconductor device

and fabless suppliers.

Form factor drives WLFO

In applications requiring advanced

silicon node technology, the chips will

generally shrink, which, in turn, pushes

the package transformation from fan-in

wafer-level chip-scale package (WLCSP)

to WLFO to accommodate the routing of

higher pin counts. In analog products for

mobile applications, conventional lead

frame and/or polymer-based packages

have often been converted to WLCSP

or WLFO on account of form factor and

manufacturing cost considerations. Today,

there are a variety of companies, including

Xiaomi, IMC, Qualcomm, and PMIC,

commercializing WLFO packaging.

These companies are producing a variety

of packaging sizes from 3mm to 15mm

to meet device packaging requirements.

Typical package sizes for WLFO range

from 3mm x 3mm to 10mm x 10mm for

low- to mid-range devices, while package

size for leading-edge semiconductor chips

can exceed 15 x 15mm.

Why is this conversion happening?

Popular smartphones are constrained to

a certain size, but battery capacity, and

consequently battery size, are getting

bigger. This means that the remaining

motherboard area allotted for chips has

remained unchanged, yet consumers

are demanding more novel smartphone

functionality. Disruptive packaging

technologies are critical to saving space

and meeting consumer demand for higher

performing devices.

Beyond smartphones, wafer-level

fan-out packaging is being used in the

automotive market to help enable active

safety systems such as blind spot detection

and radar modules. NXP, Freescale

and Infineon have demonstrated their

products and/or prototypes in the market

for advanced driver assistance systems

(ADAS), all using a 10mm package size

or smaller.

Cost benefit drives PLFO

The primary motivation for panel-

level packaging schemes such as panel-

level fan-out (PLFO) is more die in a

larger area format for cost advantages. In

contrast to the 300mm diameter wafers

used in WLP, the conventional panel

sizes in panel-level fan-out are large—

approximately 3 times larger than wafers,

which creates huge opportunities for

economy of scale. In the case of substrate

packages, assembly houses are working

with the substrate suppliers who run the

panels as starting format and supply strips

singulated from the panels to the assembly

houses. Strips are used because much of

the manufacturing infrastructure developed

for conventional packaging handle strips

of various sizes. For example, wire

bonders and flip-chip bonders can handle

a maximum of 100x300mm strip size.

As well known in the packaging industry,

the material contribution of the substrate

comprises approximately 30% to 60+%

of the entire packaging cost, therefore

reducing substrate cost plays a large role in

reducing overall cost. That is why OSATS

and integrated device manufacturing

(IDM) packaging groups are keenly taking

a look at the bigger panel processing.

T

TECHNOLOGY TRENDS