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9

Chip Scale Review January • February • 2018

[ChipScaleReview.com]

Challenges of ECD panel fan-out in high volume and

potential solutions

By Jon Hander, Demetrius Papapanayiotou, Robert Moon, Arthur Keigler, Michelle Schulberg, Mani Sobhian, Bryce Chen,

Tyler Barbera, Cristina Chu

[TEL Advanced Packaging]

u l t i - c h i p p a c k a g e s

using fan-out assembly

t e c h n i q u e s c o n t i nu e

to approach the size and performance

offered by heterogeneous through-silicon

vias (TSVs) at a fraction of the cost.

The electronics industry has historically

delivered cost reductions, as well as

performance improvements at a steady

pace, and manufacturers are still striving

t o supply lowe r pr ice s for 300mm

wafer-based fan-out substrates than

are currently available. This situation

has slowed the adoption of fan- out

technology in high-volume commercial

p r oduc t s s uch a s mobi le dev ic e s ,

processors, and memory. Migration from

300mm wafer substrates to larger 510

x 515mm panel substrates could deliver

the cost-down required for high-volume

adoption of fan-out technologies, but the

technical challenges associated would

have to be overcome.

When plated Cu feature sizes shrink,

thinner seed layers are required to

electroplate trenches and vias. This results

in a terminal effect, a new challenge for

panel-level plating that is well-known in

wafer-level processing. The terminal effect

can cause increases in Cu thickness near the

electrical contact zone in an electrochemical

deposition (ECD) tool resulting in poor

cross-panel uniformity. Some wafer-

level solutions for the terminal effect can

be applied to panel ECD tools, but their

efficacy can be diminished on account of the

scale and shape of the panel. Two solutions

that show promise are the adoption of multi-

zone anodes and the placement of dummy

structures near the contact terminals.

Within-die uniformity becomes more

challenging as feature sizes shrink and

more complex design rules change feature

shape morphology. Wafer-scale chemistries

make the fabrication of the finer fan-out

features possible, but adoption of these

requires complete isolation of anodes.

Organic additive packages that actively

compensate for local layout variation can

be used to deliver within-die uniformity

improvements. One drawback of these

advanced chemistries is that they are by

nature more reactive and can degrade

over time. In wafer-level processing, Cu

chemistry typically represents about 30-

40% of the total cost of an ECD deposition

step. Plating costs can be minimized and

process control can be extended over the

life of the plating baths by using plating

cells with ion-exchange-membranes. A

transition from 300mm wafer-scale fan-out

production to a panel scale would require

the use of membranes for stability and

cost savings. TEL Advanced Packaging

believes that the ECD process will not be a

barrier to high-volume fan-out panel-level

packaging manufacturing.

Introduction

TSV has been a viable advanced

packaging technology for several years

[1]. The technical advantages of TSV

are compelling, but our industry is still

seeking lower price-to-performance

ratios for packaging solutions for high-

volume commercial products. Fan-out is

one solution for multi-chip packages that

is growing faster than

originally predicted on

account of its significant

cost advantages.

F i g u r e 1

s h o w s

s e v e r a l m a r k e t

for e ca s t s for g r ow t h

t w o y e a r s f r o m

a n y g i v e n d a t e . A

c ompa r i s on of t h r e e

s e t s o f e s t i m a t e s

shows t h a t on eve r y

occasion TSV growth

w a s p u s h e d o u t

a n o t h e r t w o y e a r s

a n d a d j u s t e d d ow n ,

while fan- out g rowth

increased dramatically.

I n t h e c a s e o f TSV,

forecasted growth early on was high

because of the technical capabilities

t h i s p a ck a g i ng me t hod of fe r s . I n

subsequent years however, forecasts

s l u m p e d a s t h e c o s t a n d a f e w

technical issues stagnated the growth

outlook. This trend is similar to the

f r ont- end - of-l i ne low- k d iele c t r ic

outlook in the late nineties. In that

c a s e , d i e l e c t r i c m a t e r i a l s we r e

originally projected to be the leading

solution for RC constant reduction.

The ba r r ie r s t o t h is st r at egy we re

uncovered, and the t ransition f rom

aluminum to copper emerged as the

solution at the 130nm generation [2].

Fan- out ha s ex ist ed a s a si ngle -

chip packaging solution for roughly 20

years [3]. With recent adoption of the

technology, it has emerged as a low-

cost, multi-chip solution. Performance

and scaling improvements are not quite

as significant as those offered by TSV,

but the cost and ease of integration make

fan-out more attractive for moderate

cost high-volume commercial products.

Figure 1

shows fan-out market forecasts

have increased eightfold since 2012 while

the TSV market forecast has decreased.

M

Figure 1:

Comparison of market expectations for TSV and fan-out from 2012–2017.