Chip Scale Review January • February • 2018[ChipScaleReview.com]
Wa f e r- l e ve l f a n - o u t p a c k a g i n g
represents a substantially lower price
point compared to TSV , but it is
still cost prohibitive for many products
especially for mult i- ch ip packages
that are typically greater than 20mm
in size. An increase in substrate size
has been one way the integrated circuit
(IC) industry has delivered significant
cost reductions historically . Fan-
out technologies would enable this
trend to continue at the package level
even though wafer subst rates seem
to have reached a plateau at 300mm.
Panel substrates 510 x 515mm in size
represent a g reater than th ree -fold
increase in substrate area for less than
a 50% increase in cost. This multiplier
in number of die or packages per substrate for panel compared to
wafers increases as the size of the unit grows. This is particularly
important for multi-chip fan-out structures, which by their nature
are larger than single-die packages. This is plotted in
6mm die up to 32mm die.
The cost reduction is compelling for a transition from a 300mm
wafer to a 510 x 515mm panel, but meeting the technology
requirements now and in the future  for high-yielding panel-
level fan-out must be proven. Cu line formation is one of the more
demanding applications prohibiting the transition from wafer- to
panel-scale fan-out manufacturing. High density interconnect (HDI)
printed circuit board type panel-scale electroplating tools can support
a 10µm line/space (L/S) feature size, but 5µm L/S is now required.
Also gaining traction in the next few years, multi-chip fan-out
technical requirements will include a feature size reduction from
10 to 2µm L/S and cost reduction achieved through a substrate
transition from wafer to panel substrates. For this reason, the design
features commonly found on wafer-level ECD tools will need to
be ported to panel-scale equipment. Thin-seed plating hardware
(<5000Å) compatible with advanced chemistries will be critical to
deliver improved within-die performance.
Thin seed plating
There is a trend towards greater heterogeneity in advanced packaging
structures, which leads to pattern and density variations that present
challenges to uniform deposition across the panel substrate. Concurrently,
the market is moving towards smaller features, which require thinner
seeds. However, these thinner seeds can pose greater uniformity challenges
for deposition because there are higher resistances in thin seed plating
that lead to greater terminal effect. Two strategies can combat these panel
plating challenges: 1) multi-zone anodes, which provide the capability to
fine tune currents on specific areas of the panel, and 2) the use of dummy
die, which move higher deposition areas away from active die.
The terminal effect is a phenomenon that occurs due
to the resistance of the seed layer on the substrate. There are typically
localized higher current densities at the edge compared to the center.
These higher current densities lead to thicker deposition.
As linewidths shrink below 10µm, Cu seed layer thicknesses in ECD
must reach sub-micron levels. This transition causes what is known
as a terminal effect, where the thickness near the contact area has a
significantly lower resistance than the areas located farther from the
contacts resulting in increased ECD thickness. This phenomenon is
Multi-zone anodes provide the ability to adjust current
density to fine tune deposition to specific sections of the panel to accommodate a
variety of patterns.
The terminal effect in conjunction with changes linked to the dummy die near the edge
of the wafer can cause large shifts in the plated Cu thickness near the contact region.
shows the variation in near-edge film thickness for a thin-seed and thick-seed
condition. Because the productivity of panel-scale ECD tools for multi-chip fan-out is so
high, it is unlikely that there will be enough manufacturing demand for dedicated process
tools that can be statically configured to support a single seed thickness or dummy
structure. Therefore, there is a need to dynamically adjust the ECD cell to provide
uniform plating thickness independent of seed thickness or dummy structure.
One way to deliver this dynamic tuning capability is with multi-zone anodes.
Multi-zone anodes provide the ability to adjust the current density within a certain
area of the substrate independent of current crowding effects observed with shielding.
Multi-zone anodes also offer the flexibility to make panel-to-panel adjustments or
even achieve a desired plated thickness profile during the plating of a single panel. A
five-zone anode array may be arranged as shown in
Productivity comparison of a 300mm wafer with a 510 x 515mm panel
for various die/package sizes.
Current density profile across 250mm half-panels (i.e., from center of
panel to edge) plated at the same average current; 30µm seed and 0.2µm seed.