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12

Chip Scale Review January • February • 2018

[ChipScaleReview.com]

The nonuniformity is pronounced (both

within-panel and within-die). Also, the

figure highlights the marked impact of

within-panel nonuniformity on within-die

coplanarity; this interaction is obviously

more pronounced for larger (packaged) die.

Figure 8

shows the same array, plated

under the same conditions, but with a

horizontal and vertical dummy pattern along

the outside edges. The areas in blue show

the photoresist, while the adjacent areas in

white are targeted for plating. The addition

of a dummy pattern increases the proportion

of how much of the overall area of the panel

will be plated. This figure demonstrates

how the topography in the region of interest,

the product-dice area, becomes more

consistent across the panel. Terminal and

current crowding effects are corrected. The

dummy structures deliver a greater than

5x improvement in

uniformity in addition

t o a c o p l a n a r i t y

i mp r oveme n t t h a t

provides higher yields.

The cost of using

of dummy structures

to improve process

control is significantly

l o w e r o n 5 1 0 x

515mm subs t r at e s

than 300mm wafers

on a unit area basis.

The area advantage of

panels is significant,

and provides a 30-

50% reduction in cost

per die, which is the

main driver for any

substrate size increase.

Large die, or packages,

are more conducive

to fitting in panel geometries without

the productivity losses associated with a

wafer’s circumference.

Figure 9

shows

a comparison of percent die loss when a

10mm dummy structure is incorporated into

wafer- and panel-scale fan-out processing

for different die sizes. Aside from the

intrinsic cost savings associated with a

larger substrate, the added cost of dummy

structure placement on a panel can be up to

twice as much for a wafer.

Advanced chemistries

Within-die coplanarity (or general

uniformity) specifications become more

demanding as the number of metal layers

increases. These tightening specifications

coupled with larger density spans from

smaller features represent a substantial

reduction in plating rates, or call for the

adoption of a more reactive additive

package. Inherently more reactive additives

require specially-built ECD hardware to

minimize the breakdown of the additives,

which can cause poor yields, extended

maintenance times, and increase costs.

As features become smaller and pattern

densities increase, the performance of the

plating chemistries becomes an increasingly

important factor in meeting product

specifications. Many of the more capable

additive suites are also more sensitive to

decomposition byproducts and require

careful process control.

While the specific byproduct formation

pathways vary depending on the chemical

nat u re of specif ic add it ives, many

additives react adversely to anodes in the

plating bath, either during electrolysis or

when the cell is idle. Therefore, isolation

of the anode from the bulk plating bath

is often advantageous. Ion exchange

membranes and discreet anolyte and

catholyte chemistries can be an effective

way of meeting isolation requirements.

By-product management

Ion exchange membranes prevent the

reaction of organic additives with Cu

anodes, the evolving oxygen associated

with insoluble anodes, or direct oxidation

at either type of anode. Chemistr y

selection can once again be based on

process performance criteria, rather than

considerations of undesired additive

breakdowns at the anode or substrate.

Ac cele r at or a nd levele r a r e t wo

common classes of organic additives

used in Cu electroplating for advanced

packaging. Breakdown of these additives

occurs in the presence of Cu, which

is useful at the substrate, but not at

Figure 9:

Calculation of die lost as a function of substrate and die size.

Figure 7:

Simulation of plating of a 9 die x 9 die array. Note: Z height topography

exaggerated for visual clarity. Plate-able area of projected die is shown in yellow. The

solid blue color corresponds to photoresist.

Figure 8:

Same die array as in

Figure 7

but with added patterned dummy structures

at the outside edges of the quadrant.