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Chip Scale Review January • February • 2018


3D IC heterogeneous integration by FOWLP

By John H. Lau

[ASM Pacific Technology Ltd.]

n t h i s s t u d y , t w o 3 D I C

heterogeneous integrations by fan-

out wafer-level packaging (FOWLP)

technology are presented. The emphasis of

the first such method is on the design, and

of the other method, the emphasis is on the

manufacturing method.


Moore’s law [1] has been driving the

system-on-chip (SoC) platform. Especially

in the past 10 years, SoCs have been very

popular for smartphones, tablets, and the

like. SoCs integrate different-function

ICs into a single chip for a system or

subsystem. Two typical SoC examples

are shown in

Figure 1

. The application

processor A10 is designed by Apple and

manufactured by TSMC using its 16nm

process technology. It consists of a 6-core

graphics processor unit (GPU), two dual-

core central processing units (CPUs), 2

blocks of static random access memories

(SRAMs), etc. The chip area is 125mm



The application processor A11 is also

designed by Apple and manufactured using

TSMC’s 10nm process technology. The A11

consists of more functions, including a tri-

core Apple-designed GPU, etc. However,

the chip area is about 30% smaller than

that of the A10 because of Moore’s law,

i.e., the feature size is from 16nm down

to 10nm.

Heterogeneous integration

Why is heterogeneous integration of

such great interest? One of the key reasons

is because the end of Moore’s law is fast

approaching and it is more and more

difficult and costly to reduce the feature

size (to do the scaling) to make SoCs.

Heterogeneous integration contrasts

with SoCs as follows. Heterogeneous

integration uses packaging technology to

integrate dissimilar chips with different

functions from different foundries, wafer

sizes, and feature sizes (as shown in



) into a system or subsystem, rather than

integrating most of the functions into a

single chip and going for a finer feature

size. For the next few years, we will see

more of a higher level

o f h e t e r o g e n e o u s

integration, whether

i t i s f o r t i m e - t o -

market, performance,

fo r m f a c t o r, powe r

consumption, signal

i n t e g r i t y, o r c o s t .

H e t e r o g e n e o u s

integ ration is going

to t ake some of t he

ma r ke t s h a r e away

f rom SoCs on high-

end applications such as

high-end smartphones,

t able t s , we a r able s ,

networking devices,


a n d c o m p u t i n g

devices. How should

these dissimilar chips

t a l k t o e a ch o t he r,

however? The answer

is: redistribution layers

(RDLs)! How should

those RDLs be made?

In this study, we use

FOWLP technology.

3D IC heterogeneous integration by


T h e A10 a n d A11 a p p l i c a t i o n

processors are packaged using TSMC’s

InFO (integrated fan-out) wafer-level

packaging method [2-5]. The mobile

dy namic r andom acce ss memor ie s

( DR AMs) a r e w i r e b o n d e d o n a

3-layer core-less package subst rate

and the substrate is area-array solder

b a l l e d o n t o p o f t h e a p p l i c a t i o n

processor package – a package-on-


Figure 1:

SoC platforms for the A10 and A11 application processors.

Figure 2:

Heterogeneous integration or SiP.

Figure 3:

PoP for packaging the application processor and mobile memory.