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Chip Scale Review January • February • 2018


Laser debonding processes enable wafer-level

packaging advances

By Thomas Uhrmann, Boris Považay, Mathias Pichler, Florian Schmidseder, Daniel Burgstaller

[EV Group]

emp o r a r y wa f e r c a r r i e r

technologies have gai ned

con side r able impor t a nce

in the semiconductor industry over the

past several years in response to the

increasing adoption and proliferation of

new packaging architectures, including

stacked (3D) packaging, to suppor t

increased device f unctionalit y. The

initial approach to 3D-packaging using

through-silicon vias (TSVs) that allow

the functionalization and stacking of thin

device structures has experienced slower-

than-expected adoption due to relatively

high process costs. As a result, only a

few high-performance devices with TSVs

have thus far passed the threshold to

mass manufacturing. More cost-sensitive

applications have driven the development

of alternative integration processes better

suited to their cost requirements. Fan-

out wafer-level packaging (FOWLP), in

particular, is well-suited for a majority of

mobile applications due to its ability to

simultaneously address performance, form

factor and cost needs. Other devices, such

as those in the radio frequency (RF) space,

also followed this trend, enabling RF

front-end functionality of band selection,

filtering and amplification modularized

within a single package, thereby reducing

cross talk and RF compatibility issues

in mobile devices [1-3]. Whereas early

FOWLP devices contained individual

dies with the need to expand area for

redistribution, in recent years, FOWLP

became a universal packaging platform.

Tempo r a r y wa fe r bond i ng i s a n

essent ial step to suppor t advanced

packaging approaches, such as FOWLP,

by enabling the mounting of product

wafers onto carrier wafers for wafer

thinning and back-side build-up, or

to serve as a processing platform for

redistribution-layer (RDL) first processes.

FOWLP process f lows typically fall

under two basic integration categories,

called chip-first and chip-last. With the

chip-first approach, individual chips

are embedded into epoxy

mold, forming freestanding

mold wafers as a basis for

redistribution and bumping.

This process is frequently

refe r red t o a s embedded

wafer-level ball grid array

(eWLB). I n t he ch ip -la st

app r oa ch , r ed i st r ibut ion

l a y e r s a r e p r o c e s s e d

f i rst, before t he d ies a re

individually attached and

over-molded. In both process

f l ows , t emp o r a r y wa fe r

carrier technologies play a

crucial role. For chip-first (or RDL-last),

temporary carriers are used for package-

on-package (PoP) technology, where

thinning device wafers below 400µm

does not allow for the use of freestanding

mold wafer handling, as discussed by

Campos, et al. [4-6]. Here, temporary

carrier technology is used to handle thin

wafers throughout the full redistribution

process. Slide off debonding has been

found to work reliably within the mold

wafer process flow. Contrary to this, chip-

last is a pure build-up process, where the

temporary bonding step forms the base

layer. The package is built successively

on top of the car rier wafer, and UV

laser debonding is the final process step

separating the devices from the carrier.

Therefore, fundamental knowledge of

critical process parameters for UV laser

debonding is key to ensuring a high

overall process yield.


Figure 1:

Selection of temporary bonding processes differentiated by

application, temperature stability and debonding temperature.

Figure 2:

Classification of temporary bonding and debonding processes.