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Chip Scale Review January • February • 2018


Total control of the bump process to ensure reliability

of stacked devices

By Matt Wilson

[Rudolph Technologies, Inc.]

s e l e c t r o n i c d e v i c e s

b e c o m e e v e r m o r e

p e r v a s i ve i n o u r d a i l y

l i ve s , e n s u r i ng t h e i r qu a l i t y a nd

r e l i a b i l i t y h a s b e c ome n o t j u s t

desirable, but in some cases, a life

or death requirement—consider the

possible consequences of a catastrophic

fa i lu re i n a med ical dev ice or t he

control system of an autonomous car.

Electronics manufacturers are under

growing pressure to build quality and

reliability into their devices and that

pressure is magnified by the increasing

c r i t i c a l i t y o f t h e a p p l i c a t i o n s .

Although this is not a new demand,

it is made more challenging by the

a p p e a r a n c e o f n e w p r o c e s s a n d

pa ck ag i ng t e ch nolog ie s t ha t pa ck

greater functionality into less space

th rough ver tical integration. All of

these technologies require connections

in the third dimension, above or below

the die, thus adding, quite literally,

a new dimension to inspection and

metrology requirements.


Consumer tolerance for device failure

is at an all-time low, as they demand more

functionality and more convenience from

their electronic devices. The results of

failure range from minor inconvenience

– a wait in a long line because a dead cell

phone could not retrieve a boarding pass

– to catastrophe from a failed pacemaker

or wrecked car. The automotive industry

is an excellent example. Its relentless

focus on reliability is driven not only by

the cost of failure in human terms, but

also by market forces such as costly recall

and foreign competition implications.

When cars contained only a few electronic

components, a failure rate of one in a

million might have been acceptable.

Autonomous cars may each have tens

of thousands of electronic components,

making one-in-a million not nearly

good enough.

Vertical integration

The microelectronics industry has

followed a familiar narrative since its

birth—put more computing power and

functionality in less space; only now

it has entered, quite literally, a new


Packaging these vertically-integrated

die requires the need to provide interlayer

con ne c t ion s t hat a r e a s sma l l a nd

reliable as the multilayer interconnect

technolog ies used wit h i n t he ch ip.

Th is need for ver t ical connect ions

h a s c r e a t e d a whole new cl a s s of

technologies – advanced packaging –

with a whole new lexicon of terms (and

acronyms): through-silicon vias (TSVs),

redistribution layers (RDLs), bumps,

pillars, nails, under bump metallization

(UBM), wafer-level packaging (WFP),

fan-in, fan-out, and many more. All

these technologies serve the purpose of

providing reliable, electrically isolated,

vertical connections, and most, at some

point, involve the creation of a conductive

“bump” protruding through an insulating

layer to carry the signal to the next layer

above or below.

Total bump process control

As these bumps have become smaller

and denser, fabricating them reliably has

required the adoption of process control

technologies, including extensive inspection

and metrology. Total bump process control

refers collectively to the 2D/3D inspection

and metrology requirements of this class of

technologies. Controlling these processes

is critical to ensuring the reliability of the

finished device and requires the combination

of standard 2D techniques with a new class

of 3D technologies. As dimensions shrink,

repeatability and resolution requirements

will increase, surpassing the capability of

white light techniques and requiring the

use of laser-based technologies. But total

bump process control requires more than

just new sensors, it requires a comprehensive

approach using advanced analytics—

distilling classified, usable results from

the torrent of raw data created by these

new technologies. As shown in

Figure 1


software to visualize bump coplanarity

gives users a powerful tool to quickly assess

various bump heights within a set tolerance.

In addition, inspection and metrology

systems must have the flexibility to control


Figure 1:

Coplanarity wafer map visually alerts users when bump height tolerances are too high or too low.