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Chip Scale Review January • February • 2018

[ChipScaleReview.com] Surface analysis as a “blueprint” for semiconductor package manufacturing Jaimal Williamson Texas Instruments 28 Total control of the bump process to ensure reliability of stacked devices Matt Wilson Rudolph Technologies, Inc. 32 Reducing wafer test time Klemens Reitinger ERS electronic GmbH 36 The “More than Moore” semiconductor industry is changing the transportation paradigm Jérôme Azémar, Guillaume Girardin, Yohann Tschudi Yole Développement 39 Epoxy adhesives: mechanical versatility by design Jonathan Knotts, Daniel Morgan Creative Materials, Inc. 43 23 Laser debonding processes enable wafer-level packaging advances Thomas Uhrmann, Boris Považay, Mathias Pichler, Florian Schmidseder, Daniel Burgstaller EV Group

CONTENTS

Volume 22, Number 1

The International Magazine for Device and Wafer-level Test,

Assembly, and Packaging Addressing

High-density Interconnection of Microelectronic IC's including

3D packages, MEMS, MOEMS,

RF/Wireless, Optoelectronic and Other

Wafer-fabricated Devices for the 21st Century.

STAFF

Kim Newman Publisher knewman@chipscalereview.com Lawrence Michaels Managing Director/Editor lmichaels@chipscalereview.com Debra Vogler Senior Technical Editor dvogler@chipscalereview.com

CONTRIBUTING EDITORS

Roger H. Grace - MEMS rgrace@rgrace.com Dr. Ephraim Suhir - Reliability suhire@aol.com Steffen Kröhnert - Advanced Packaging Steffen.Kroehnert@amkor.com

EDITORIAL ADVISORS

Dr. Andy Mackie (Chair)

Indium Corporation

Dr. Rolf Aschenbrenner

Fraunhofer Institute

Joseph Fjelstad

Verdant Electronics

Dr. Arun Gowda

GE Global Research

Dr. John Lau

ASM Pacific Technology

Dr. Leon Lin Tingyu

National Center for Advanced Packaging

(NCAP China)

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Chip Scale Review (ISSN 1526-1344) is a registered trademark of

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FEATURE ARTICLES

(continued)

E-Tec Interconnect AG,

Mr. Pablo Rodriguez, Lengnau Switzerland

Phone : +41 32 654 15 50

, E-mail: p.rodriguez@e-tec.com