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Chip Scale Review January • February • 2019

[ChipScaleReview.com]

eterogeneous integration

uses packaging technology

to integrate dissimilar chips

with different functions from different

fabless houses, foundries, wafer sizes, and

feature sizes into a system or subsystem.

This situation differs from solutions such

as system-on-chip (SoC), in which most

functions are integrated into a single chip

using a finer feature size. For the next few

years, we will see more of a higher level of

heterogeneous integration, whether it is for

time-to-market, performance, form factor,

power consumption, signal integrity, and/

or cost [1]. How should these dissimilar

chips talk to each other, however? The

answer is redistribution layers (RDLs). In

this study, the fabrications of RDLs for

heterogeneous integrations are presented.

Emphasis is placed on the RDLs for

heterogeneous integration on: A) organic

substrates, B) silicon substrates (through-

silicon via (TSV)-interposers), C) silicon

substrates (bridges), and D) fan-out

substrates. Some recommendations will be

provided. System-in-package (SiP) is very

similar to heterogeneous integration, except

heterogeneous integration is for finer pitches,

more inputs/outputs (I/Os), higher density,

and higher performance. The subsections

below follow the alphabetic labels above.

A: RDLs for heterogeneous

integration on organic substrates

In the past few years, tremendous

efforts have been devoted to enhance/

advance the capabilities of conventional

low-cost high-density substrates and

build-up organic package substrates by

increasing the number of build-up layers,

fabricating thin-film layers on top of the

build-up layer, shrinking the dimensions

of the metal line width and spacing, and

reducing the pad size and pitch.

A1: IBM’s SLC technology.

More

than 25 years ago, IBM in Japan at Yasu

invented the surface laminar circuit (SLC)

technology (

Figure 1

[2-4]). SLC formed

the basis of today’s very popular low-cost

organic package substrates with build-

up layers vertically connected through

microvias [5] to support heterogeneous

integrations such as f lip chips. There

are two parts of the SLC technology:

one is the core substrate and the other is

the SLC for the signal wiring. The core

substrate is made by the ordinary glass

epoxy panel. However, the SLC layers are

sequentially built up with the dielectric

layers made of photo-sensitive epoxy and

the conductor plane of copper plating, i.e.,

using a semi-additive process (SAP). In

general, a package substrate with twelve

layers [e.g., two core layers and ten build-

up layers (5-2-5)] and a 10µm line width

and spacing are more than adequate to

support most of the chips.

A2: Shinko’s build-up with thin-

film layer.

In 2013 and 2014, Shinko

proposed making thin-film layers (down

to 2µm) on top of the build-up layer of a

package substrate and called it “i-THOP”

s ubs t r at e [6 ,7 ] i nt ended for h igh -

performance applications. (See [8] for

more details.)

A3: Cisco’s organic i nterposer.

Figure 2

shows a 3D heterogeneous

integration designed and manufactured

with a large organic interposer with

fine-pitch and fine-line interconnections

by Cisco [9]. The organic interposer

has a size of 38mm x 30mm x 0.4mm.

The mi n imum li ne width, spaci ng,

and thickness of the f ront side and

back side of the organic interposer are

the same and are, respectively, 6μm,

6μm, and 10μm. It is a 10-layer high-

density organic interposer (substrate)

and the via size is 20µm. The major

manufacturing steps for making the

organ ic i nter poser are the same as

those for the organic build-up package

substrate. These include [9]: a) plating

th rough-hole (PTH) generation and

H

By John H. Lau

[ASM Pacific Technology, Ltd.]

Redistribution layers for heterogeneous integrations

Figure 1:

Heterogeneous integration on organic substrate (IBM SLC).

Figure 2:

Heterogeneous integration on organic substrate (Cisco organic interposer).