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Chip Scale Review January • February • 2019


his article proposes Moore’s

Law for Packaging to replace

Moore’s Law for ICs, as this

is seen as coming to an end. Moore’s

Law for ICs is about scaling transistors

to ever smaller sizes, from node to node

and interconnecting and integrating

these to result in more transistors in

smaller chips with higher performance

at lower cost from 300mm wafers. As

transistor scaling and integration comes

to an end due to physical, mater ial

and elect r ical limit at ions, Moore’s

Law for Packaging can be viewed as

interconnecting and integrating smaller

chips with the highest transistor density

and the highest performance at the lowest

cost. Additionally, the proposed law can

encompass smaller system components

to form 2D, 2.5D and 3D multi-chip

modules in the short term, and 3D system

architectures in the long term for the

entire system. Package or system scaling

is proposed to be one and the same as the

end goal of packaging is a system.

Just as Moore’s Law for ICs has two

components — number of transistors

and cost of each transistor — I propose

that Moore’s Law for Packaging have

two components as well: the number

of interconnections or inputs/outputs

(I/Os), and the cost of each I/O. This article

lays the ground work for Moore’s Law

for Packaging by showing how I/Os have

evolved from one package family node

to the next, starting with <16 I/Os in the

1960s to the current silicon interposers

with almost 200,000 I/Os. A variety of

ways to extend Moore’s Law by advances

in Si interposers and beyond, using glass

in panel embedding is also proposed. As

Moore’s Law for electronic packaging

comes to its own end, this article proposes

3D opto-electronic packaging as the next

Moore’s Law for Packaging.


Moore’s law has been the driving force

behind transistor scaling and integration

as well as reduction in cost of transistors

during the last six decades. Electronic

systems, however, such as smartphones,

self-driving electric cars and machines

mimicking human brains, are more than

transistors and ICs. Moore’s Law for ICs,

which includes both increased transistor

integration and cost reduction every two

years, has brought electronics to more

than a trillion-dollar industry. However,

the prediction is that it will come to an

end, at least in cost, if not in transistors.

So what will take its place for electronics

systems of the f ut u re? This ar ticle

proposes Moore’s Law for Packaging

or Interconnections to replace Moore’s

Law for ICs, at least in terms of cost

in the short term. Reducing transistor

size — referred to as transistor scaling

— along with their interconnections

and integration to ever higher transistor

density, was the basis of Moore’s Law for

ICs. Component size reduction for both

active and passive system components,

referred to as system scaling, along with

their interconnections and integration

to form modules in the short term and

systems in the long term, can become

Moore’s Law for Packaging to form

packaged systems.

Ju s t a s Moo r e’s Law c omp r i s e s

doubling of transistors and a simultaneous

cost reduction from node to node, every

18-24 months, Moore’s Law for Packaging

must do the same. Interconnections have

been driven by computing systems, and

within computing systems, between logic

and memory. The new era of artificial

intelligence, mimicking human brains, is

yet another reason for Moore’s Law for

Packaging or Interconnections to come to

the fore.

Currently, the most advanced Moore’s

Law for Pa ckag i ng i s wit h wa fe r-

ba s ed si l icon pa ck ag i ng. Si l icon -

based packaging, however, has many

limitations at material, substrate or

interconnect and system levels. At the

material level, its electrical loss and its

dielectric constant are very high. At

the interconnect level, its capacitance

and resistance are very high, leading

to so-called RC delays, slowing system

performance f rom node to node. In

addition, Si-based packaging doesn’t

conform to Moore’s Law for cost. Cost,

of course, is the basis for going away

from Moore’s Law for ICs. At the system

level, Si interposers, while perfectly

matched to ICs in terms of their thermal

coefficient of expansion (TCE), they are

totally mismatched to system boards,

thereby requiring additional packaging,

and subsequently making system-level

interconnections even longer.

Moore’s Law for ICs

Moore’s Law states that the number

of transistors on a silicon chip double

approximately ever y two years [1],

as shown in

Figure 1a

. Moore’s Law

has been proven to be accurate for six

decades and is thus used to set R&D

targets in the semiconductor industry.

However, due to physical transistor

scaling and leakage limitations [2,3],

Moore’s Law cannot be sustained forever.

As the transistor size gets smaller, the

distances between transistors also get

smaller. The size of transistors would

reach molecular dimensions eventually.

At that point, the electrons would tunnel

through the short distances, leading to

short circuits [4,5]. Therefore, there is a

limit beyond which Moore’s Law for ICs

is not possible — called the “beginning

of the end of Moore’s Law” — this is

expected to be reached within the next

decade. The second part of Moore’s Law

has to do with cost. Moore’s Second Law

states that the manufacturing cost must

decrease as the number of transistors per

unit area increase from node to node from

a given size of wafer. The semiconductor

industry has concluded, however, that

beyond 14nm, there was minimal or

no cost reduction as the next node was

introduced [2] (see

Figure 1b



Moore’s Law for Packaging to replace

Moore’s Law for ICs

By Rao R. Tummala

[Georgia Institute of Technology]