Chip Scale Review - January February 2020

14 Chip Scale Review January • February • 2020 [ChipScaleReview.com] tool to capture die placement error data from a panel and feeds that information forward. The “feed-forward” solution optimizes the stepper, site-by-site, for X, Y and rotation offsets, during exposure. Visualization of the metrology data allows the user to characterize upstream and downstream processes. Moreover, analytical capabilities predict yield as a function of exposure field size, thereby allowing the user to balance throughput against yield in real time. This solution can sig n i f icantly i nc rea se st eppe r throughput, reduce cost and increase productivity while ensuring high yield. Die placement challenges Ge ne r a t i ng r e c on s t i t u t e d p a ne l subst rates creates t ranslational and rotational die placement errors. The “pick and place” process itself introduces initial errors that are exacerbated during the mold process, and by instability of the mold compound throughout repeated processing cycles. With redistribution layer (RDL) features currently achieving d i me n s i on s a s sma l l a s 2µm , d i e Overcoming FOPLP die placement error By Keith Best [Onto Innovation] t is well understood that advanced packaging applications require high performance, low cost, increased functionality and improved reliability that 2.5D and 3D packaging solutions provide. Fan-out panel-level packaging (FOPLP) is one of the technologies that has the potential to meet these packaging requirements. Similar to fan-out wafer- level packag i ng ( FOWLP), FOPLP processes reconstitute die on a substrate, in this case a rectangular platform that can be significantly larger than the standard 300mm diameter wafer form. In the reconstitution process, die are displaced from their nominal grid locations during the epoxy molding compound process a nd some t ime s du r i ng subs equent processing steps. This fan-out technology delivers more space for redistributed I/O connections, providing increased flexibility for homogeneous and heterogeneous integration. Importantly, the larger panel format can support more packages per substrate than the 300mm wafer form, and the final package size can be increased by adding space between the die. Although FOPLP processing has many advantages, it also faces signif icant challenges. One critical challenge is die placement error, which occurs when die are positioned during the reconstitution and molding process. These placement errors are amplified with the larger panel format when compared to reconstituted wafers, and er rors of 50μm or more are not unusual. In order to guarantee acceptable yield, these errors must be corrected during the lithography process using site-by-site corrections. Conducting metrology and site-by-site exposures on the lithography system is very time consuming. Substrate alignment and error correction may be calculated using global alignment, but this correction does not accommodate nonlinear die placement errors. It has become clear that only site-by-site corrections can deliver the overlay required to maintain good yield. Executing site-by-site alignments in the stepper reduces throughput and increases cost enough to make that approach to FOPLP processes impractical. A new approach uses an external metrology I Figure 1: The optimized stepping process loop includes: 1) measurement of die displacement errors outside the stepper; 2) Site correction calculations/yield modeling; and 3) exposure.

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