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10

Chip Scale Review July • August • 2017

[ChipScaleReview.com]

Gearing up TSVs to solve next-generation application

challenges

By Bruno Morel

[aveni]

fter a long and arduous journey

from research and development

to commercialization, through-

silicon vias (TSVs) are now being used in

semiconductor devices to form electrical

interconnections in the vertical direction

(2.5D and 3D), generally between multiple,

often heterogeneous, layers. Sensor

applications that use TSVs include CMOS

image sensors (CIS), which occupy the

lion’s share of the TSV market, and newer,

specialty applications like fingerprint sensors.

Additionally, memory applications that use

TSVs—namely, high-bandwidth memory and

hybrid memory cube devices—are moving

into volume production. These stacked

memory devices offer higher performance

vs. planar layouts and increased capability,

especially when combined with other

components to serve the graphics-processing,

data-processing and server markets.

Concurrently, TSVs are making headway in

the automotive industry, with increased use

in various microelectromechanical systems

(MEMS) and sensors.

Some semiconductor manufacturers

still expect that TSVs won’t move beyond

niche applications due to remaining

roadblocks, such as thermal issues and

the subsequent stress-related reliability

issues with stacking memory on logic,

as well as cost constraints. For now, at

least, they have redirected their efforts

toward alternate solutions, such as fan-

out wafer-level packaging (FOWLP) at

low densities, and hybrid bonding without

TSVs at high densities.

However, because of the performance

improvements offered by devices using

TSVs, we anticipate steady adoption in

more applications, leading to significant

volume increases. According to industry

analysts, TSV markets are expected to

show continued growth, particularly in

high-performance computing applications

such as the growing server market. This

article discusses some of the drivers,

challenges and benefits involved in

fabricating and implementing TSVs.

Alternatives to TSVs

Although it’s tr ue that FOWLP is

taking off, thanks primarily to Apple

adopting TSMC’s integrated fan-out

(InFO) technology in its A10 processor,

it does have limitations. Cur rently,

FOWLP technologies in manufacturing

achieve 5µm line/space (l/s) densities.

High-density FOWLP, such as Amkor’s

SWIFT™ and SLIM™, have achieved

2µm l/s features, but these have yet to be

commercialized. Efforts are underway to

extend high-density FOWLP to system-in-

package (SiP), and ultimately to interposer

applications, in which a high-density fan-

out model is attached to a substrate as an

alternative to TSV 2.5D.

FOWLP is undoubt ed ly a st rong

competitor in heterogeneous applications

involving CMOS image sensors and

MEMS devices because high density is

not a requirement. However, this is not

the case for high-performance computing

server applications and heterogeneous

stacking of memory on logic because of

the l/s limitations. Essentially, FOWLP

is disqualified for applications requiring

higher-density interconnects in the sub-

1µm range.

Another technology being touted as a

cost-effective, high-density alternative

to TSVs is Cu-Cu/oxide hybrid bonding,

invented and patented as Direct Bond

Interconnect (DBI

®

) by Ziptronix. DBI

joins the dielect r ic regions and the

metal interconnect regions on each of

two wafers, providing both mechanical

support and dense electrical interconnects

between the wafer pair. Demonstrated

at an interconnect pitch of 2µm, DBI is

said to be scalable to the lithography and

alignment manufacturing capabilities

of any application [1]. Additionally,

depending on the achievable wafer-to-

wafer bond accuracy, it is believed that

pitches to 1µm will be possible [2].

In 3D backside-illuminated image

s e n s o r s , DBI p r ov ide s a low- co s t

alternative to TSVs, as it combines the

permanent bonding and interconnect

steps into one. Indeed, it could become

the technology of choice to replace fusion

bonding on account of its ability to make

electrical contact and its superior electrical

and mechanical properties [3]. However,

DBI requires face-to-face interconnection

of the bond pads, and therefore it is limited

to a two-wafer or two-die stack. It should

be noted, however, that work has been

done to extend Cu-Cu direct bonding to

incorporate TSVs. Imec reports success

implementing 5μm-diameter, 50μm-deep

via-middle TSVs to connect the hybrid

bonded wafer interfaces to the external

wafer backside [4].

Among the biggest benefits of TSV

interconnects are the signal densities that

can be achieved. In general, the distance

a signal has to travel along a wire (or

interconnect path) is directly related to

power usage. TSVs serve to shorten the

signal path between the die, allowing the

system to run faster while using less power

[5]. Shorter wires decrease the average

load capacitance and resistance and

decrease the number of repeaters needed

to regenerate signal on long wires, thereby

improving signal density [6].

In applications with interconnect

densities in the sub-1µm range and

requiring more than two stacked wafers

or die-to-wafers, TSVs are currently

the only commercially available option.

As the server market growth trajectory

continues to soar, the volumes of advanced

packages implementing high-density TSV

interconnects will increase exponentially.

Building a case for high-aspect-

ratio TSVs

As CMOS scaling continues in logic

devices and we see the likes of Intel, TSMC

and Samsung ramping to 10nm and 7nm

processes, the need for high-aspect-ratio

(HAR) TSVs for stacked devices becomes

more critical. Stacking at advanced nodes

necessitates a sub-micron technology that is

similar to the dimensions of the upper metal

A