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17

Chip Scale Review July • August • 2017

[ChipScaleReview.com]

Wafer thinning for advanced packaging applications

By Laura Mauer, John Taddei, Scott Kroeger, John Clark

[Veeco Precision Surface Processing]

riven largely by the growing

n e e d f o r m o r e d a t a ,

i nc rea sed f unct ional it y

and faster speeds, consumer electronic

devices have sparked a revolution in IC

design. As it becomes increasingly more

expensive and technically challenging

t o scale down t he feat u re si ze s i n

semiconductor devices, Moore’s law is

yielding to the concept of “More than

Moore,” which is driving integrated

functionality in smaller and thinner

packages. According to market research

firm Yole Développement, advanced

packaging will represent 44% of all

semiconductor packaging services while

reaching estimated revenue of $30 USD

billion by 2020—up f rom $20 USD

billion in 2014 [1].

2.5D and 3D packaging have become

c r it ical t o new product s requ i r i ng

h ighe r pe r formance and i nc rea sed

functionality in a smaller package. The

use of through-silicon vias (TSVs) has

been discussed as a method for stacking

die to achieve vertical interconnects.

However, the high costs associated

with this technology have limited TSV

use to a few applications such as high-

bandwidth memory and logic, slowing

its adoption within the industry to only

those applications that exact a premium

price for the superior performance of

TSV architecture. Lower-cost advanced

packaging concepts have been developed

and are now in production for those

applications that do not require ultimate

per formance. Recently, alter nat ive

methods for exploiting the z-direction

have tur ned to variations of fan-out

wafer-level packaging (FOWLP), which

do not include TSVs.

In many of these concepts there is a

need to thin the wafer to remove all of

the silicon while being selective and

not etching a variety of other f ilms

underneath that include oxides, nitrides

and metals. In addition, there can be

temporary bonding adhesives and mold

compounds encapsulating the chips,

which must remain undamaged. This

paper discusses the use of wet etch for

wafer thinning processes needed for

advanced packaging, including new

FOWLP applications.

Introduction

Wa f e r t h i n n i n g h a s b e c ome a

critical enabling process in advanced

p a c k a g i n g f o r a w i d e v a r i e t y o f

device types. Beyond high-bandwidth

memor y a nd log ic dev ice s , wh ich

requi re thi nni ng to enable ver tical

stacking with TSVs, wafer thinning

i s a l so c r it ica l for ma nu fa c t u r i ng

m i c r o e l e c t r ome ch a n i c a l (MEMS)

d e v i c e s , wh i ch t y p i c a l l y c on t a i n

a s e n s o r e l e me n t , a c a p a n d a n

application-specific

i nt eg r at ed ci rcu it

(ASIC). In the case

of MEMS, all three

w a f e r s m u s t b e

thinned to achieve

t he r e qu i r e d si z e

r e d u c t i o n f o r

packaging. CMOS

i m a g e s e n s o r s

employing via-last

p r o c e s s i n g mu s t

also be thinned to

s u p p o r t s m a l l e r

f o r m f a c t o r s ,

w h i l e b a c k s i d e

illuminated CMOS

image sensors must

b e b a c k- t h i n n e d

to less than 10µm in order to open

up the photosensitive sensor area for

enhanced sensitivity. Thin wafers (in

the 60-70µm range) are also needed

for power devices to improve their

cu r rent-car r ying capabilit y, reduce

on-resistance, and minimize power

consumption.

I n g e n e r a l , t h e r e a r e f o u r k e y

requirements in wafer thinning. First,

t he bu l k of t he sil icon is removed

by wafer grinding, which can take a

t ypical 700 -800µm thickness wafer

d ow n t o 10 -5 0 µm . S e c o n d , i t i s

necessar y to remove the subsurface

damage and residual stress in the wafer

that results from the grinding process.

Otherwise, this damage can lead to die

cracking during singulation. Third, the

surface of the wafer must be smoothed

to eliminate g r ind marks. Both the

stress/damage removal and smoothing

process are typically done using either

chemical mechan ical plana r i zat ion

(CMP), or wet etch processing.

Figure

1

illustrates the benefits of utilizing

we t e t ch t o e l i m i n a t e s ub s u r f a c e

damage and relieve stress following

the grinding process. Finally, these

requirements must be met in a cost-

e f f e c t i ve ma n n e r a s t h e y a r e a l l

additive to the overall cost of the wafer.

Beyond t he gene r al need s l ist ed

above, TSV reveal and FOWLP have

additional wafer thinning requirements.

I n 3D/TSV i nteg rat ion, t he silicon

wafer needs to be thinned to reveal the

Cu TSVs so that 3D connections can be

made. Fast silicon etch rate and good

etch uniformity are key requirements

f o r T SV r e v e a l , i n a d d i t i o n t o

smoot h su r face f i n ish i ng and cost

effectiveness. At the same time, the

etch process must avoid any removal of

the SiO

2

liner or Cu TSV. The cost and

performance benefits of using a single-

wafer wet etch process with adjustable

D

Figure 1:

Wet etch relieves stress and eliminates subsurface damage.