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26

Chip Scale Review July • August • 2017

[ChipScaleReview.com]

Advanced process control solutions for fan-out

wafer-level packaging

By Dario Alliata, Philippe Gastaldo, Yann Guillou, Gilles Fresquet

[UnitySC]

and

Jean-Philippe Piel, Sylvain Petitgrand

[Fogale Nanotech]

ith the increase of costs,

delays and complexity at

the most advanced front-

end silicon technology nodes, advanced

packaging has become a key differentiator

for achieving next-generation requirements,

and thereby continued sustainability in

the semiconductor industry. Within the

advanced packaging realm, fan-out wafer-

level packaging (FOWLP) is gaining

momentum due to its high integration,

extreme flexibility, performance enablement

and cost advantages, compared with more

conventional assembly technologies.

Despite the wide adoption of FOWLP

during the last few years, there are

several challenges remaining about the

industrialization of the process. For example,

regardless of the FOWLP methodology used,

the epoxy molding compound (EMC) is still

a potential source of issues, with challenges in

total thickness variation (TTV) management,

package warpage and die shift. From a pure

metrology perspective, the EMC thickness

measurement may also be a challenge,

because the epoxy material typically becomes

opaque above a certain thickness and cannot

be measured in the visible or infrared

domains by conventional optical metrology

techniques.

In this article, we introduce the various

metrology technologies used to control

the FOWLP process and review the main

metrology measurements required during

high-volume manufacturing. Additionally,

we explore the advantages of using an in-

line, integrated 2D/3D metrology solution to

characterize the FOWLP fabrication process

using the chip-first/face-down approach.

FOWLP manufacturing flow and

metrology considerations

In the classical embedded wafer-level ball

grid array (eWLB) approach [1], the silicon

chips are probed, thinned and singulated

during the FOWLP process. These chips are

then placed on an adhesive tape that sits on

a temporary carrier using standard pick-and-

place equipment. The packaging is completed

through the following main process steps:

wafer molding, carrier removal, passivation/

redistribution layers (RDLs), balling and

dicing. Each step presents some challenges,

and metrology solutions are required to

minimize their impact on the final yield.

Tape lamination and pick-and-place

When the tape is laminated onto the

temporary carrier, keeping the TTV of the

adhesive layer under control minimizes

coplanarity issues when the known-

good die (KGD) are picked and placed.

Figure 1

shows the TTV for an adhesive

l aye r on a 300mm S i ca r r i e r. The

measurement was performed by mapping the

whole wafer area with 127 points by spectral

interferometry in transmission mode.

One important performance issue for

FOWLP is determined by die placement

on the substrate. The two operations that

most affect die location error are the die

placement operation and die migration

during the compression molding process.

The first contribution is essentially coming

from the precision/repeatability of the pick-

and-place equipment and by the method

of operation used. If a unique die type is

positioned over the carrier, the single-gantry

mode is typically used. To combine different

functionalities (e.g., die types) into the same

final package, multiple gantries must be

applied. The single-gantry mode typically

would affect only the position of each die

with a constant offset, whereas multiple-

gantry mode would introduce potentially

multiple offsets [3]. Line scan 2D/3D

confocal chromatic technology was used to

verify the X, Y position and tilt of each die.

Figure 2

shows the 3D rendering view on a

carrier populated with a single family of dies

by using the 4See Series inspection platform.

(Note: The 4See Series used 2D/3D line-scan

confocal chromatic technology to inspect

the whole wafer surface for defectivity and

metrology.) Controlling the X/Y position of

the dies and retrofitting the information to the

pick-and-place equipment is demonstrated

to be one of the most efficient solutions to

recover the drift in the process, allowing for

the wafer to be reworked if the die position is

not within the expected tolerance.

Molding

Molding KGDs with EMC is one of the

most challenging fabrication steps in FOWLP

because it can impact the coplanarity and

planar position of the embedded dies, as

well as the warpage of the reconstructed

wafer once the carrier is removed. Die shift

affects the alignment of the RDL on the die

pad and challenges the photolithography

process, while an excess in warpage prevents

the possibility of handling the reconstructed

wafer with the fabrication equipment. Both

potential hazards are caused by thermal

expansion of the carrier and mold shrinkage

upon cooling. Typically, the impact on those

parameters can be anticipated by controlling

the thickness and TTV of the EMC layer

across the wafer, as well as its surface

roughness. EMC thickness measurement is

not trivial because the material properties

W

Figure 1:

a) (left) Sequence of measured points;

and (right) 2D wafer map of adhesive layer

thickness distribution.

Figure 2:

3D view of KGDs sitting on the carrier.