Previous Page  35 / 52 Next Page
Information
Show Menu
Previous Page 35 / 52 Next Page
Page Background

33

Chip Scale Review July • August • 2017

[ChipScaleReview.com]

A comprehensive high-density advanced packaging

solution for today’s OSATS and foundries

By Keith Felton

[Mentor]

he i nc r e a s i ng g r ow t h of

i n novat ive IC pa ckag i ng

technologies, such as fan-out

wafer-level packaging (FOWLP), multi-

substrate/multi-device packages like 2.5D

with interposers and system-in-package

(SiP), is in response to system scaling

demands and the increasing demand for

heterogeneous integration. However,

these emerging technologies are creating

new challenges because they commonly

employ silicon-like features and processes,

or multi-substrate architectures to facilitate

high-performance memory devices such as

high bandwidth memory/hybrid memory

cube (HBM/HMC).

Today’s package design methodologies

and tools are at an inf lection point.

The entry of silicon foundries into the

packaging supply chain further disrupts

tools and methodologies with their

application of silicon process design

kits (PDKs) and verification processes

t o pa ck ag i ng. Thu s , h ig h - de n sit y

advanced packaging (HDAP) design

and verification require cooperation and

collaboration between design houses,

OSATS, foundries, and electronic design

automation (EDA) vendors. What’s

needed is a solution comprising fully

integrated tools and the functionality

to operate in both the IC and packaging

domains. Also, developing and deploying

process-optimized design kits such as

accessory development kits (ADKs) and

PDKs, the OSATS, foundries, and their

customers can achieve design, fabrication,

and assembly predictability and package

performance. This article will cover the

implementation of an optimal end-to-end

HDAP methodology addressing the needs

of OSATS and foundries.

The move to HDAP

The term “high-density advanced

packaging” (HDAP) was coined by

Mentor to categorize the disr uptive

packaging technologies that present unique

challenges to traditional design tools and

methodologies (

Figure 1

). The most well-

known and publicized form of HDAP is the

fan-out wafer-level packaging (FOWLP)

that is rapidly gaining popularity in the

fabless semiconductor market. FOWLP

was given broad public attention through

TSMC and its InFO FOWLP process, but

there are other suppliers offering proven

FOWLP processes. The other common

HDAP package types are 2.5D using silicon

interposers, chip-on-wafer-on-silicon

(CoWoS), and wafer-on-wafer (WoW).

HDAP's use of “IC-like” processes and

tools necessitates a higher data resolution

and design rule checking (DRC) accuracy

for smaller feature sizes. GDSII quality and

performance on non-Manhattan geometries

can also be an issue for t raditional

packaging tools. I/O counts on application-

specific integrated circuits (ASICs), field-

programmable gate arrays (FPGAs), and

system-on-chips (SoCs) can approach or

surpass 10K pins, which impact design tool

performance, capacity, and throughput.

HDAP as a new technology “node point”

requires a substantially different design

flow, similar to how the organic laminate

(plastic) ball grid array (PBGA) substrate

was a “node point” evolution, which

gave rise to new design flows, tools, and

processes. Differences between today’s

well-understood PBGA flow and HDAP

(

Figure 2

) present some unique challenges

to existing design tools, methodologies, and

processes. Examples include:

• P r o t o t y p i ng a nd c on ne c t i v i t y

planning of multi-die integration

a nd op t i m i z a t ion (c r it ic a l fo r

interposer-based designs);

• Device and substrate stacking – 3D

interoperability;

• Shrinking feature sizes and new

geometries;

• Place and route support for through-

silicon via (TSV), micro-bumps,

silicon inter poser redistribution

layer (RDL), and signal routing;

• Increasing pin counts on devices

T

Figure 1:

HDAP can be characterized by multi-substrate/multi-device packages that require device/substrate

stacking using high pin-count devices or designs.