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Chip Scale Review July • August • 2017


Integrated solid-state capacitors based on carbon


By Vincent Desmaris, Rickard Andersson, Amin Muhammad Saleem

[Smoltek AB]

h e c o n s t a n t d ema nd f o r

m i n i a t u r i z a t i o n , a d d e d

functionality and increased

pe r formance of elect ron ic dev ice s

systematically drives higher integration

by adding more devices and functionality

on a single chip. Over the last 40 years,

this has been achieved by scaling CMOS

technology according to Moore’s law,

resulting in better power performance and

cost per function for each technology node.

As the feature size of CMOS devices now

approaches quantum or physical limits, the

downscaling of devices is slowing down

and therefore cannot sustain the lowering

of cost and performance per function

alone. As a result, a new component

packaging strategy called heterogeneous

integration, focusing on the performance

enhancement and cost reduction at the

system level, provides a new dimension

and enabler to follow Moore’s law in terms

of system performance, by the stacking

of chips (3D) or using an intermediate

substrate, the interposer (2.5 D).

The full deployment of the 3D or 2.5D

packaging technologies requires on-

chip or in-package capacitors, not only

in traditional integrated circuits, but

also for integrated components, possibly

on interposers, for applications such as

decoupling capacitors, voltage stabilization

or RF filters. In parallel, the emergence

of the Internet of Things (IoT) is right

around the corner, requiring not only high

capacitance per unit area for the operation

of the devices, but also integration of

efficient and smart solutions with moderate

energy storage and harvesting to operate

the individual autonomous devices [1].

Traditionally, electrochemical double-

layer capacitors (EDLC) [2] are devices

prov id i ng t he h ighest capacit ance/

footprint area [3], using the physical

adsorption and electrostatic accumulation

of ionic charges at the surface of the

electrodes, originating from a liquid or

sol-gel electrolyte [4]. However, liquid

electrolytes are often toxic and corrosive,

and t hei r encapsu lat ion present s a

considerable challenge that hinders their

integration directly onto CMOS chips.

Consequently, integrated high density

capacitors need to be fully solid-state in

order to meet the requirements of stability

and lifetime. Fully solid-state capacitors

have faster charge and discharge rates

compared to a liquid electrolyte capacitor

(supercapacitors), making them more

useful for high-frequency applications.

Be side s bu l k y c e r amic d i s c r e t e

capacitors, the simplest realization of a

capacitor is the parallel plate capacitor

u si ng a t h i n (a few nanomet e r s i n

thickness) solid dielect r ic layer. In

this configuration, the capacitance is

proportional to surface area, hence the

parallel plate capacitors are limited by

their footprint area. In ICs, an effective

increase of the capacitance area has been

achieved using deep trenches in the silicon

substrate using dielectrics deposited using

low-pressure chemical vapor deposition

(LPCVD) [5] or multilayers of atomic

layer deposition (ALD) [6]. Fur ther

increasing the capacitance requires

consuming precious space on the chip, or

other cost-increasing and partially reliable

methods, in particular irreversible very

deep reactive ion etching (DRIE) of the

substrate combined with atomic layer

deposition. This limits the potential for

implementation of integrated capacitors.

Recently, IPDiA (now Murata) has shown



capacitors integrated in the

silicon interposer at the cost of a minimum

etch depth of 100µm [7] that potentially

weakens the interposer’s mechanical

stability or imposes a large thickness of

the interposer.

With the similar idea of increasing the

surface area of the capacitor electrodes

in mind, carbon nanostructures have

been investigated as electrode materials

in combination with thick dielectric

layers deposited by ALD. However, such

an approach has been, so far, limited

by the necessity of transfer ring the

nanostructures from the substrate on

which they are grown to the active area,

where they have to be used, because of

the growth temperature required by such

structures. Capacitors based on transferred

ca rbon nanot ubes (CNT) g rown at

700ºC, subsequently coated by a 10-15nm

dielectric deposited by ALD provided

capacitance values of about 40nF/mm



The recent progress and availability of

our proprietary technology has allowed

the growth of vertically aligned carbon

nanof ibers (CNF) at a temperat u re

compatible with CMOS technology

d i rectly rooted on t he act ive ch ip,

underlying substrate or component.

This technology also allows the process

on any substrate that can sustain a

thermal budget of less than 400°C, and

permits the realization and re-visiting

of integrated solid-state capacitors with

high-capacitance per footprint area. More

specifically, integrated novel capacitors

can be made of vertically aligned carbon

nanofibers as one electrode material,

providing a large 3D surface area for

a small footprint, and their conformal

coating of dielect ric and a metallic

counter electrode. The more than tenfold

enhancement of the active su r face,

compared to the occupied footprint on

the chip, where they are rooted, makes

ver y eff icient use of the chip. Such

capacitors can therefore take advantage

of the unique combination of the intrinsic

electrical and surface properties of carbon

nanostructures [9], without the economic

and technical hindrances of the transfer

process after growth, associated with the

limited and laborious nature of such a

transfer process.

Our enabling technology for the growth

of the CNFs is catalytic plasma-enhanced

chemical vapor deposition (PECVD)

[10] (

Figure 1

), which made possible a

completely deterministic and possibly

reworkable method to produce CNFs on

substrates. The positioning of the fibers

on a substrate would depend on the