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Chip Scale Review July • August • 2017


High-performance and low total device cost using

2.5D packaging

By C. Key Chung, Wen Shan Tsai, Daniel Ng, C.F. Lin, Ally Liao, Steward Pan

[Siliconware Precision Industries Co., Ltd.]

em i c ondu c t o r p a ck a g i ng

using 2.5D technology has

demonstrated high-performance

with low total cost. Though in its infancy,

this packaging is believed to become

mainstream with respect to the assembly

industry roadmap. It is gaining ground and

soon will grow significantly, thereby enabling

an alternative to Moore’s Law scaling.

Meanwhile, 2.5D technology also brings a

significant decrease in cost compared with

system-on-chip (SoC) devices, which will

also be discussed in this article.


The development of the semiconductor

industry has followed Moore's Law for

more than 60 years. The law – in its current

iteration – states that the number of integrated

transistors on an integrated circuit (IC)

chip is doubled approximately every 18

months. However, as technology nodes have

progressed to below 10nm, the cost per die

size (mm) becomes enormous and difficult to

sustain. Various news reports have said that

the physical limitation of the transistor gate

oxide — now at single digits in nanometers

— caused a CPU provider to delay its

10nm node implementation to 2017 [1].

Additionally, foundry fabs face the challenges

associated with the technical limitations and

yield challenges after implementing 10nm

process technology [2]. The fundamental

consideration of performance over cost to

keeping up with Moore's Law is now nearing

its limits and has been heavily debated by

semiconductor industry forecasters [3-5]. The

major topic now is: Has Moore's Law really

come to its limit, or can it be continued, in a

manner of speaking, using other means? This

paper presents the continuation of scaling

(though not in the traditional sense of Moore’s

Law) that happens in assembly manufacturing

using 2.5D as an illustration.

Continuing “scaling” with 2.5D


Moore's Law predicts that the performance

or transistor density on an integrated circuit

chip will be doubled every 18 months. With

the technology node narrowing down to

10nm and below, it reaches to near-term

limits. The investment for new equipment

and facilities becomes exceedingly high

and demand for high yield determines the

success of this single digit node scaling.

Below the 10nm node, current leakage and

dielectric breakdown are difficult to control:

there are only a few electrons within a cell,

which makes the operating voltage and the

noise within cells very difficult to address

[6]. The low yield of foundry fabs [2], and

the delayed implementation of the 10nm gate

oxide [1] announced in 2015 reflect these

challenges. Higher investment cost combined

with a lower quantity per wafer due to low

yield, amplifies the cost per die as depicted


Figure 1

[7]. This situation inadvertently

has slowed transistor scaling progress.

Our recent research finds that 2.5D

packaging [8] is a way to continue Moore’s

Law by integrating heterogeneous logic

and memory dies together so as to deliver

higher elect r ical per formance. The

package design has 100x improvement in

inter-die bandwidth/

wat t; 50% power

savings; 5x latency

reduction, and 20x

denser wire pitch [9].

More importantly,

a lower total device

c o s t w i t h mu c h

better yield can be


We should reflect

on what we consider a

somewhat surprising

development: 2.5D

packaging costs are

high, and though

debated intensively,

we now come to a

different conclusion.

C e r t a i n l y, 2 . 5D

packaging by itself

as compared to other

packaging is costly.

However, when we compare its cost to the

electrical performance of a device, the cost

benefit is obvious. We need to emphasize that

the device here is a micro-system within a

package, or a system-in-package (SiP).

Commercial products integrate the

microprocessors and stacked memory in

a single package using a through-silicon

interposer (TSI) (

Figure 2

). The TSI provides

not only similar performance as compared to

the system-on-chip (SoC), but also a better

cost advantage. The reason for this is that the

integrated microprocessor and other logic

dies that are part of the SoC require a larger

die size. One cannot compensate for this

situation by scaling down the transistor size

significantly. Technology nodes at 10nm and

below require a huge investment, particularly

in the lithographic process. The larger die

size will exacerbate a lower yield, thereby

increasing the cost per die. This does not

bode well for the economics.

In addition to the above considerations,

the fabrication processes for microprocessor

and memory devices are not compatible

and cannot be integrated. Thus, 2.5D


Figure 1:

Cost per die trend with technology node [7].

Figure 2:

2.5D IC structure schematics.