Chip Scale Review - July August 2018
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Chip Scale Review July • August • 2018


Advanced chip-package-board co-design

By Tom Whipple, Narayanan TV


he proliferation of packaging

d e s i g n s t h a t c o m b i n e

multiple chips into a single

package is creating new challenges for

package, printed circuit board (PCB)

and integrated circuits (IC) designers.

The common practice of designi ng

the package, PCB and IC in st and-

alone env i ronment s requi res t ime -

consuming manual processes that are

error-prone and limit the potential for

design reuse. What is needed are 3D

co-design tools that integrate planning

and final design implementation at the

system level for PCBs, ICs, packages

and mechanical enclosures. The ability

t o conduct syst em-level co - de sign

makes it possible to optimize bump and

ball placement, I/O placement and pin

assignment to lower chip, package and

PCB layer counts even in nontraditional

structures with routing complexity in

both vertical directions. The emerging

IEEE 2401 design file format standard

goes one step further by offering the

potential to st reamline the process

of communicating design data with

customers and partners using different

electronic design automation (EDA)

tools or with third-party software.

New packaging architectures

driving innovation

The continual increases in feature

density that have driven innovation in

the semiconductor industry for 50 years

appear to be on the verge of slowing

or coming to a halt. For example, Intel

has suggested silicon transistors can

only keep shrinking in accordance with

Moore’s Law for another five years [1].

As the potential for improvements in

front-end processing slows, electronics

or ig i nal equ ipment manu fact u re r s

(OEMs) are seeking innovations in back-

end processing, turning to a wide range

of new packaging solutions to pack ICs

ever more tightly together.

For example, package-on-package (PoP)

architectures are increasingly used to

connect logic RAM ICs with short

interconnects (

Figures 1, 2

). Higher

density packaging methodologies

such as system-in-package (SiP)

integrate multiple chips into a

single package, par ticularly in

mixed digital and radio frequency

applications. Even more complex

packaging technologies utilize

th rough-silicon vias (TSVs) to

reduce interconnection distance

in multi-chip package designs in

order to increase per formance

and reduce power consumption.

For example, fan-out wafer-level

packaging (FOWLP) establishes

die-to-die and die-to-ball grid array

(BGA) connectivity directly through

packaging redistribution layers

(RDLs), eliminating the packaging

substrate used in more established

flip-chip (FC) and wafer-level chip-

scale packages (WLCSPs). Samsung

Electro-Mechanics' fan-out panel-

level packaging (FoPLP) [2] places

the chip on top of a panel board,

eliminating the need to use PCBs for the

package substrate, which reduces the cost

of production.

Challenges facing IC, PCB and

package designers

The g reat e r complex it y of t he se

and other new packaging solutions,

c o m b i n e d w i t h t h e i n c r e a s i n g

functionality of single package modules,

is creating vast new challenges for not

only package designers, but also IC

and PCB designers who must integrate

t he pa ck age i nt o t he i r own wo r k .

Traditionally, the IC team creates the

IC, the board team designs the PCB,

and the package team is responsible

for get t i ng t he PCB and IC t eams

talking to each other. The increasing

functionality, tighter cost constraints,

a nd t he de c r ea si ng form fa ct or of

today’s elect ronics products means

that components need to be tightly

coordinated with each other so that

pin assignments can be optimized for

small size and minimum layer count


Pa ckage de sig ne r s a r e t y pica l ly

responsible for determining the optimal

number of packaging layers, routing

the RDL on the IC side and the escape

rout e on t he PCB side. They must

consider bump and ball placement, I/O

placement and pin assignment to lower

chip, package and PCB layer counts.

This task is particularly diff icult in

non-traditional structures with routing

complexity in both vertical directions

such as PoP and SiP. With packaging

densit y i nc rea si ng at a r apid r at e,

packages are becoming increasingly

d if f icu lt to route, wh ich i ncrea ses

design time and, in some cases, has a

negative impact on system performance.

Th is raises t he quest ion of how to

plan out pin assignments, component

placement, escape routing, etc., for

these complex designs.


Figure 1:

A fan-out wafer-level two-ASIC package with a six-

memory package on top designed using Zuken’s IC package

and PCB layout tool, CR-8000 Design Force.

Figure 2:

A 3D-IC stack side-by-side with a memory device

in a package.