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Chip Scale Review July • August • 2018


Some EDA ve ndo r s a dd r e s s t he

challenges noted above by offer ing

feasibility or planning tools that don’t

generate mask-ready layouts. These

tools, however, are often difficult to

justify when users are already spending

so much on implementation tools. It’s

also important to note that feasibility

and planning requirements change

– proce s se s cha nge, work f lows

change, roles change, etc. The use

of two separate tools increases the

difficulty of implementing change,

especially when either the planning

or implementation tool doesn’t meet

the new requirements. In addition,

translating between feasibility tools

and implementation tools is a lossy,

error-prone process.

New generation of co-design


A new gene r at ion of sys t em-

level 3D co-design tools addresses

the challenge discussed above by

providing an environment for system

design that i nteg rates plann i ng,

optimization, and implementation

of all parts of the system: 1) chip-

package-board; 2) physical design

and analysis; 3) schemat ics and

layout; 4) mechanical computer-

aided design (MCAD) and electronic

design. A h ier a rch ical dat abase

enables each person work ing on

the project to see his/her piece of

the puzzle in context of the f ull

product. Engineers can do system-

level design, full package design,

full PCB design, interposer design,

and optimize the RDL routing and

die bump placement for IC design in

a single user interface (

Figure 3


Pu sh but t on i nt eg r a t ion wit h

s chemat ic a nd simu lat ion t ool s

ensures design data is transferred

quickly and efficiently to achieve

quick turnaround. The mechanical

e n c l o s u r e d e s i g n i s c h e c k a b l e

agai nst the f i nal PCB, package,

and IC dimensions to ensu re f it

and clearance (

Figure 4

). Layout

versus schematic (LVS) verification

software validates that a particular

integrated circuit layout corresponds

to the original schematic or circuit

diagram of the design.

The need for the kind of co-design

tools discussed above is best illustrated

with the creation of a daisy chain test

configuration between two packages

a nd b e t we e n a pa ck age a nd a d ie

in a PoP design. A daisy chain test

configuration is a stitching together of

pins between two (or more) different

components to provide a nearly zero-

Ohm path between a set of pins. It is

used for a variety of tests to validate

and improve the assembly process.

These can include testing for voids,

characterizing solder bumps, measuring

coef f ic ient of t he r ma l expa n sion ,

t e s t i ng e l e c t r i c a l c o n t i nu i t y a nd

elect romig ration reliabilit y, among

other things.

Figure 5

shows the 3D

view of an example of daisy chains

between two packages in a package-on-

package configuration. It also shows

several daisy chains between a flip-

chip die and the bottom package.

Creating the f ull system-level

netlist for this example is a tedious

and error-prone process with most

tools because it involves set ting

up proper net connections on the

chip (or package) on one hand, and

setting up a package on the other.

This situation translates to not only

maintaining the logic on the chip

side and package, but also verifying

the logic across the chip-package

interface. This process can become

p a r t i c u l a r l y ch a l l e ng i ng wh e n

dealing with designs in silos and

in a two-dimensional environment,

wherein, while one can edit and

visualize in the individual designs,

visualizing the daisy chain across

design boundaries is not possible.

The user then has to ensure that

the logic is implemented correctly

from the start and that the proper

verification is put in place.

However, when using a tool such

as CR-8000 Design Force, which is

naturally a 3D, hierarchical design

system, the visualization is easily

accomplished through an easy-to-

use utility to create and visualize

complex daisy chain configurations.

The chain is created or modified by

selecting a set of pins and running

the command. The netlist for both

sets of pins is created (or updated)

and the routing for both substrates

is created. The other need would

be to provide a means for passing

such information to other tools. For

example, if one needed to pass the

above daisy chain to an electrical

simulation tool or a mechan ical

simulation tool, cu r rent process

would need to rely on passing each

of the individual designs separately,

r a t h e r t h a n a s a s y s t em . T h i s

reinforces the need for an exchange

format capable of passing 3D data

across tools, which forms the focus of

the next section.

Figure 3:

Three-die stack with through-silicon-vias (TSVs) on an

interposer in a package on a board using CR-8000 Design Force.

Figure 4:

Three boards with 3D components and a 3D camera

enclosure designed using CR-8000 Design Force.

Figure 5:

3D view of daisy chains across a chip-package and a

PoP chip designed using CR-8000 Design Force.