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Chip Scale Review July • August • 2018


Increasing importance of data


The i nt eg r at ion of plan n i ng and

implementation does not eliminate the

need to interface with other tools. Even

if a company focuses primarily on one

vendor’s EDA tools, inevitably, they

have customers, third-party vendors,

partners, etc., that use different sets of

tools. Or the team uses one set of tools

now, but in the past used a different tool.

PCBs and ICs are still designed with

different tools and this gap needs to be

bridged. New design techniques such

as FOPLP bring demands that current

toolsets cannot meet. In other words, the

increasing integration of EDA tools does

not eliminate the need for data exchange.

Some EDA vendors have devoted

minimal resources towards data exchange

on account of perceived costs and risks.

The primary benefits provided by the

EDA vendor a re i n t he algor it hms

and features of its tools. The design

resou rces requi red to suppor t dat a

exchange take away from development

of the core software. The development

costs are required to support industry

data exchange formats and maintenance

expenses can be considerable because

of frequent changes to these formats.

The inter pretation of data exchange

formats can be difficult. For example,

it’s not uncommon for DEF files from

one vendor to be unreadable by another

vendor’s tools. EDA vendors may also

be concerned that if data can easily be

exchanged between different tools then it

will be easy for designers to move away

from their tools. With users demanding

the smooth flow of data between tools,

however, it’s clear that tools that can

provide integrated chip-package-board

f lows along with implementation and

seamless exchange of data will provide

the greatest value to designers and be the

most likely to succeed in the marketplace.

There are many de facto file formats

that are used today to share data –

spreadsheets, LEF/DEF, GDSII, ODB++,

OpenAccess, etc. – but these tools are

only supported for a subset of the whole

design. In an ideal world we would have

one standard format for all data exchange

bet ween d i f fe rent t ool and de sig n

platforms. This format may already exist

– the IEEE-2401 standard. The IEEE-

2401 standard has the potential to provide

all the information needed for design

and simulation in much less time than

is required by current methods while

being easy to implement because data

is delivered in human readable, open

formats such as XML and Verilog-HDL.

The IEEE-2401 standard enables cross-

discipline design teams to exchange

s y s t em- l e ve l n e t l i s t s , c omp on e n t

information, design rules, etc., while

avoiding the need to use error-prone

formats such as spreadsheets. The IEEE-

2401 standard format is constructed from

six basic information types including

Project Management (M-Format), Netlist

(N-Format), Component (C-Format),

Design Rule (R-Format), Geomet r y

(G-Format) and Glossary.


T he i n c r e a s i ng c ompl ex i t y a nd

density of today’s designs, combined

with the proliferation of multi-chip

packaging architectures has escalated

the challenges involved in designing

electronic products. Traditionally, three

i ndependent design processes have

been required with point tools to design

the chip, package and PCB. Today, an

integrated chip/package/board co-design

e n v i r o n m e n t

provides a holistic

a p p r o a c h t h a t

makes it possible

f o r d e s i g n e r s

wo r k i n g o n t h e

chip, package and

b o a r d t o v i e w

t h e c o m p l e t e

s y s t em i n t h e i r

own environment

a n d g o f r o m

e x p l o r a t i o n

t o d e s i g n

i mp l eme n t a t i o n

i n a c o m m o n

environment. New

industry standards

s u c h a s I E E E -

2401 go one step

further by enabling

t h e i n t e l l i g e n t

exchange of design

information across

t he de sig n t e am

wh i le ma k i ng it

possible to conduct

signal and power

integrity analysis

concu r r ent ly, or

interface to best-

in-class simulation

and analysis tools from Ansys, Keysight,

CST and Synopsys, to name a few.


1. s/601441/moores-law-is-dead-now- what/

2. panel-level-packaging-the-next- sleeping-giant-and-other-thoughts- from-iwlpc-2017/


To m W h i p p l e h a s B a c h e l o r ' s

and Ma ster's deg rees i n Elect r ical

a n d Compu t e r Eng i n e e r i ng f r om

Brigham Young U. and U. of Arizona,

r e s p e c t i v e l y. He i s a S o l u t i o n s

Architect at the Zuken SOZO Center;


Na r a y a n a n TV h o l d s a Ph D i n

Electrical Engineering from Georgia

Institute of Technology, and an MS in

Advanced Materials from Singapore-

MI T A l l i a n c e . He i s a So l u t i o n s

A r ch it e c t at Zu ken SOZO Cent e r ;