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Chip Scale Review July • August • 2018



July • August 2018

Volume 22, Number 4

Zuken’s CR-8000 PCB and package layout

design tools enable multiple chips, packages and

boards to be assembled, viewed and edited on

one canvas in either 2D- or 3D-mode. The image

shows a three-die stack on a silicon interposer

that is wire bonded to a package and placed

on a board. A simple click into any one of these

components in a hierarchy tree switches edit

context to the selected part, including its specific

technology, rules and layer stack-up.

Cover image courtesy of Zuken USA Inc.

10 Advanced chip-package-board co-design Tom Whipple, Narayanan TV Zuken 14 Metal-based wafer-level and 3D-printed packaging Doug Sparks Hanking Electronics 38 Die-attach materials and LED functional performance Gyan Dutt, Nicholas Herrick, Sathish Kumar, Pavan Vishwanath, Ranjit Pandher Alpha Assembly Solutions 19 Temporary bonding for high-temperature processing of thin glass Robert A. Bellman, Prantik Mazumder, Robert G. Manley, Kaveh Adib, Shiwen Liu, Leena Sahoo Corning Research and Development Corporation 34 More than you think: the beauty of coaxial sockets Collins Sun, Ryan Chen, Hayden Chen WinWay Technology


28 7 Guest Editorial


Tech Brief

International Directory of Wafer Probers and Probe Cards


Panel-level packaging shows great progress on large-area fan-out processing Tanja Braun, Michael Töpper Fraunhofer Institute for Reliability and Microintegration 8 Technology Trends Automotive apps are driving inspection requirements for advanced nodes CSR interviews Jeroen Hoet and Stephen Hiebert 43 Industry News Report from ECTC 2018 Sam Karikalan Broadcom Inc.

The need for faster engineering development data for 5G devices

Debra Vogler,

Sr. Technical Editor