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Chip Scale Review July • August • 2019


Enabling the new 3D architecture

By Javier DeLaCruz,

[XPERI Corporation]

he challenges of sustaining

Moore’s Law and the shift

t o a “mo r e t h a n Moo r e”

approach in the indust r y have been

discussed in considerable detail [1,2].

We have seen numerous technologies

to address both trajectories, with the

introduction of new materials, processes

a nd s t r uc t u r e s , i nclud i ng va r iou s

integration and 3D-stacking approaches.

Leading-edge CMOS image sensors (CIS)

manufacturers, for example, have utilized

wafer-to-wafer (W2W) Direct Bond

Interconnect (DBI


) bonding technology,

also known as hybrid bonding, in high

volume for several years now because

of its various advantages [3]. For other

applications, such as high-bandwidth

memory (HBM) and 3D-stacked dynamic

random access memory (3DS DRAM),

manufacturers have been reluctant to

adopt a W2W approach on account of

the required changes in design, test

and self-repair. Instead, manufacturers

have focused on die to wafer (D2W)

approaches, such as microbumps and

thermocompression bonding (TCB). Such

techniques have inherent limitations and

require expensive and time-consuming

underfill between die. Applying hybrid

bonding to such applications would

provide many benefits including lower

cost, improved reliability, lower power

consumption, and higher thermal and

electrical performance [4]. Historically,

however, DBI has been only available in

a W2W configuration. Shifting such a

bonding technology platform to a D2W

configuration, however, has implications

such as a need to address increased

particulates generated as a result of pre-

bond wafer dicing and thin die handling.

Given the numerous advantages of

W2W DBI, we have spent significant

engineering effort to develop DBI



a D2W hybrid bonding process that allows

known good die KGD) to be stacked.

With the elimination of both the underfill

layers and the accompanying die standoff,

this latest bonding process provides a

pathway for increasing the number of

die stacked from 4 and 8 high, to 12, and

even 16 high, while meeting the stringent

height requirements for various electronic

applications. In addition, the availability

of a dense interconnect solution in a

high-yielding, D2W process opens up

architectural possibilities in heterogeneous

integration for 2.5D and 3D assemblies.

Development of D2W processing

DBI a nd DBI Ult r a a r e bond i ng

platforms that allow for interconnect

densities down to 1µm in a W2W and

D2W format, respectively. In the DBI

Ult ra process, as seen in

Figure 1


the host and die wafers are chemical-


Figure 1:

DBI Ultra process flow.

Figure 2:

a) Bringing activated surfaces together; b) Instantaneous dielectric bonding upon contact; c) Metal

joining during the anneal process.