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11

Chip Scale Review July • August • 2019

[ChipScaleReview.com]

mechanical polished (CMP), cleaned,

and then activated. Wafers are then

singulated and the resulting die are

f lipped and placed upon a host wafer.

This flipping and placement is repeated

until the host wafer is fully populated.

Upon contact and at room temperature,

the dielectrics bond as seen in

Figure

2

. A s u b s e q u e n t a n n e a l p r o c e s s

st rengthens the dielect ric bond and

allows the interconnects to join.

DBI (Di r e c t Bond I nt e r con ne c t)

was introduced by Ziptronix, an RTI

spinoff, in the early 2000s. Starting

with nickel as the interconnect metal in

the mid 2000s, Ziptronix demonstrated

the first copper-based hybrid bonded

interconnects with 10μm pitch in 2009.

The company developed the technology

for wafer-to-wafer applications and

subsequently licensed it to Sony [5] in

2015 for the production of CIS in high

volumes. Ziptronix was later acquired

by Tessera Technologies, now XPERI

and the technology has been licensed to

many semiconductor manufacturers and

suppliers around the world. Early efforts

to produce a D2W hybr id bond i ng

process were hampered by low yield

due to a process sensitivity to particles

a nd t he p r open sit y fo r si ng u l a t ed

devices to have many particles.

A mere three years or so ago, the

potential for die-to-wafer applications

in 2.5D and 3D was understood, but

the challenge of yield, testability and

die handling remained a barrier. Since

2015, we have devot ed sign if icant

r e sou r c e s t o d ie - t o -wa fe r p r oce s s

development and optimization and has

si nce developed a h igh-t h roughput

production-worthy process leveraging

standard production tools and industry

infrastructure. The main features of

the current production-ready process

are shown in

Figure 1

. With a cycle

t i me a p p r o a ch i ng t h e “d r y ” p i ck

and place time of a die bonder, this

process is able to bond dies at a rate of

thousands per hour, per layer, whereas

TCB t ake s conside r ably longe r on

account of the temperature, pressure

and dwell times needed.

Addressing stacking requirements

of HBMs

A pr ime candidate for DBI Ult ra

is HBM (high-bandwidth memor y).

Cur rently available in 4 and 8 high

stacks [6], the industry trajectory is

to stack 12 [7] and even 16 high HBM

stacks. A test vehicle for this approach is

seen in

Figure 3

.

An additional benefit to the hybrid

bonding approach in HBM structures is

thermal performance, where the stack

of die thermally behave as a single

die [8].

Figure 4

shows that with the

conventional approach, the DRAM die

in the center of a stack are less capable

of dissipating heat as the die on the top

and bottom. This effect is created by

the thermal-insulating effect of several

layers of underfill material. On the other

hand, if we compare

this to a similar stack

using hybrid bonding

technology, as seen

in

Figure 5

, greater

thermal uniformity

is obser ved. These

analyses both assume

t h e r m a l p a t h s

through an interposer

and a heatsink with

2W o f p owe r p e r

l a y e r . W i t h t h i s

DBI Ultra example,

t he r e is one -t h i rd

t h e m a x i m u m -

t emp e r a t u r e r i s e

c o m p a r e d w i t h

t h e c o n v e n t i o n a l

a p p r o a c h . Mo r e

importantly, the die

in the hybrid bonding

approach are similar

in temperature with

each ot he r, wh ich

h e l p s t o r e a l i z e

s i m i l a r t i m i n g

performance between

the die. The die in the stack are generally

frequency throttled to accommodate

the slowest (likely the hottest) die in the

stack. In this case, hybrid bonding would

allow for an increase in the operating

frequency of the stack.

With the development of a production-

worthy D2W process, taller stacks of

HBM die are possible because the height

of the microbumps is eliminated. With

this approach, ultra-low-profile stacking

of 16 die is now possible, as seen in

Figure 6

. Alternatively, with the existing

thermocompression approach, the height

of the copper pillars and underfill would

not only increase the height of the stack,

but also negatively impact its thermal

uniformity. In the same manner that

CMOS image sensors paved the way for

DBI W2W bonding, HBM stacks are

poised to pave the way for DBI Ultra D2W

approaches and the resultant architectures.

Moving to true 3D design

While image sensors, RF, and memory

applications are able to benefit from the

DBI process in W2W and early D2W,

there is significant applicability of D2W

DBI in the system-on-chip (SoC) space.

Depending upon the application, there

are several ways that disaggregating

Figure 3:

HBM test vehicle.

Figure 4:

Thermal analysis of conventional 4-high HBM.

Figure 5:

Thermal analysis of DBI Ultra 4-high HBM.