Chip Scale Review July • August • 2019[ChipScaleReview.com]
A n ew a r c h i t e c t u r e t h a t t a k e s
advantage of interconnect densities that
rival the density within a die can have
benef its in performance, area, yield
and thermal efficiency. The hurdle to
overcome is designing in 3D instead
of stacking 2D designs. Elimination of
the inefficient interfaces between die,
and instead treating these connections
as if they were connections within
the same die, is what opens the door
for these benefits. Furthermore, the
abilit y to use DBI Ult ra allows for
dissimilar die sizes and test abilit y
makes this approach more accessible to
applications in SoC devices.
1. G. Q. Zhang, “The rationale and
paradigm of ‘More than Moore,’”
2. F. Von Trapp, “From the ashes of
Moore’s Law: More than Moore has
arrived,” 3DInCites, Feb. 2016.
3. “ S t a t u s o f t h e CMOS I ma g e
Sensor Industry, 2018 Report” Yole
4. G. Gao, “Development of low-
temperature direct bond interconnect
technology for die-to-wafer and die-
to-die applications—stacking, yield
improvement, reliability assessment,”
5. Sony Corp., “Sony develops the
industry’s first*1 3-layer stacked
CMOS image sensor with DRAM
for smartphones,” Feb. 7, 2017.
6. JESD235A, JEDEC Oct. 2013.
7. JESD235B, Nov. 2018.
8. A. Agarwal, “Thermal and electrical
p e r f o r ma n c e o f d i r e c t b o n d
interconnect technology for 2.5D and
3D integrated circuits,” ECTC 2017.
9. M. Lepedus, “Big trouble at 3nm,”
Semiconductor Engineering, June
10. S . B o r k a r , “ T h e f u t u r e o f
of the ACM, May 2011, Vol. 54 No. 5,
Javier DeLaCruz is VP of Engineering at XPERI Corporation, San Jose, CA, where he leads the architecture,
design, and simulation team to develop and enable successful introduction of new technologies. He has over 20
years in the field, including work at eSilicon, STATS and MACOM. He also authored over 20 patents and holds
a MS degree from Boston U., and an MBA from Babson College. Email:firstname.lastname@example.org P RoHS