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17

Chip Scale Review July • August • 2019

[ChipScaleReview.com]

business. STATS ChipPAC and Amkor

Portugal remain strongholds in eWLB.

The core FO market, therefore, will move

progressively forward in all likelihood.

I n 2 016 , TSMC p e n e t r a t e d FO

packaging with high-end applications

in mobile application processor engines

(APEs) and high-performance computers

(HPCs) in networking. This has created

a new market, the HDFO market, where

TSMC is still the only dominant player.

Signif icant growth is expected with

InFO technology for advanced mobile

and high-end computing demands in

this mega-trend driven era. TSMC is

therefore expected to ramp-up InFO

f u r t he r and pot ent ial ly double t he

current capacity. Consequently, HDFO

is dominated by APE sales and volume,

with a small por tion of low-volume

manufacturing (LVM) qualification for

HPCs mainly supplied by TSMC. There

was still no other contender in HDFO

in 2018. This market is riskier because

some considerations and leverages go

beyond packaging, and in fact, involve

both front-end choice and complicated

politics between key players, etc. With

such new market growth, FO packaging

is set to gain a significant share of the

market from either advanced substrate

(by InFO) or inter posers (by InFO-

memory on substrate) [3].

Fan-out technology evolution

Fan-out packaging technology is not

only a bridge to chip-package interaction

(CPI) mismatch in pitch size, but is

also a viable solution for heterogeneous

i nt eg r at ion of f u nc t iona l it ie s i n a

desired package dimension and design,

potentially for mmWave 5G and Cloud

data server applications.

Chip-first fan-out solutions are still well

established in the market. Since 2009,

eWLB has been the most famous FO

technology in the core market. Its long

history and device-proven qualification have

provided customers with confidence and is

continually being adopted. It is considered

a mature process for single-die packaging

and potentially a good solution for system-

in-package (SiP), with products that embed

several active dies and numerous passives

already available.

As there are several licensees, multi-

sourcing is possible. This is key for

supplying end-customers, especially for

those with high-volume needs such as

the handset market. Redistributed chip

packaging (RCP) technology has better

performance in terms of die shift, and

consequently easier photolithography

steps, as well as bet ter resolut ion.

However, it has suffered from a lack of

licensees and cost competitiveness as

compared to eWLB. Although it had some

success thanks to the NXP portfolio, it is

progressively disappearing.

TSMC maintained technology leadership

in HDFO and extended it even further with

high-volume manufacturing (HVM) InFO

package-on-package (InFO-PoP) for Apple’s

latest APEs. In addition, TSMC is rolling

out InFO on substrate (InFO-oS) for high-

performance devices in HPC applications.

Fan-out antenna-in-package (FO-AiP) has

gained the interest of FO players because

FO has well-known capabilities in core

radar. Also, with FO, the embedded RF chip

will suffer less interference. In this manner,

a new performance value can be generated

for FO-AiP. Also, FO packaging adopting

memory on substrate is possible with TSMC

and potentially PTI. This will become an

alternative to 2.5D interposers.

The key technical benefit of FOWLP

is the ability to integrate dies together

f lexibly, while remaining thin. It can

displace 2.5D inter posers with f ine

L/S FO packaging on substrate and can also

displace flip chip and advanced substrate. As

an example, in the case of the APE market,

TSMC’s InFO-APE has replaced advanced

IC substrate in all the latest iPhones, which

is significant. Fan-out (InFO) has taken

more than 13% of the mobile APE market

from advanced substrates in just 3 years—

such is the potential of this technology.

FOWLP continues to cannibalize from,

and jeopardize, advanced substrate makers,

pushing them out of business. FOWLP on

substrate is another special case. In this

case, the fan-out package is flipped over

onto a substrate and therefore a substrate

manufacturer is added to the supply chain.

In such a situation, the FO packaging cost is

comparable to flip chip, but the competing

platform is 2.5D, not flip chip. The savings

come from the removal of the Si interposer.

Ne p e s , SEMCO a n d P T I h a v e

successfully invested in and developed

FOPLP for production in 2018. New

panel-level fan-out (PLFO) production is

still immature. Nepes is entering LVM

with analog/mixed integrated circuit

(IC) and fingerprint sensor packaging.

There is HVM production by SEMCO

for Samsung’s Galaxy sma r t wat ch

(

Figure 3

), and LVM production by PTI

for MediaTek’s automotive applications.

Moving forward, the next challenge is

expected to process good development

yield for HD FOPLP production.

Te c h n i c a l c o n s o r t i a a l s o s e e

opportunities, such as the new materials,

tools, and processes involved in scaling

from wafer to panel size. Material and

equipment suppliers want to join consortia

with research institutes like Fraunhofer IZM

and A*STAR IME to prepare themselves for

the challenges in case FOPLP takes off.

Clearly, PLP must create a new production

infrastructure, as front-end equipment

cannot be reused for this purpose. PLP can

leverage WLP knowledge and infrastructure

and use it on printed circuit board/flat-

panel display (FPD)/photovoltaic industry

equipment. This is not simple, as it needs

some reengineering, but it is happening.

Supply chain

For commercialization of FOWLP

packages, the established OSATS are

ASE, Amkor Portugal (NANIUM S.A.),

JCET (STATS ChipPAC and JCAP), Deca

and nepes. OSATS that are pursuing

FO packaging capabilities are Amkor

Korea, ASE/Deca, Huatian, and SPIL.

More OSATS are becoming involved in

Figure 3:

What about Samsung’s fan-out solution? SOURCE: [1]