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18

Chip Scale Review July • August • 2019

[ChipScaleReview.com]

FOWLP; they are the main contributors

for core FO and are all targeting volume

production though still with different

developmental status [1].

The FOWLP supply chain is simpler

and controlled by experienced players

in the semiconductor industry, but it

requires collaboration at the design level,

in contrast to f lip-chip ball grid array

(FCBGA). FOWLP involves simplification

and consolidation of the packaging,

assembly and testing in a “middle-end”

type of infrastructure, where the cost of

production is essentially at the wafer fab.

For example, FCBGA needs substrate

supplier, wafer fab RDL, wafer bump, and

assembly and testing, while FOWLP only

needs assembly, wafer fab RDL, wafer

bump and testing. There is a shift in the

value chain created by FOWLP.

TSMC has been the sole contributor

of HDFO since 2016 and has adopted

a unique st rategy. It is not only an

advanced foundry for the front end (FE),

but also a high-end packaging house for

the back end (BE). This business model

will continue to lead the way to create

new value and breakthroughs. With

TSMC’s InFO being able to package

high-end APE for Apple’s iPhone, a new

market, HDFO, was generated. InFO-oS

technology is now being utilized for HPC

in LVM, InFO-MS (memory on substrate)

has been developed for servers and InFO-

AiP for 5G.

Many package technologies can be

considered as PLP, but it is FOPLP that

is attracting the most attention because

of the success and awareness of FOWLP.

This attracts players with many different

business models, including OSATS,

integrated device manufacturers (IDMs),

found r ies, subst rate manufact u rers

and f lat-panel display (FPD) players.

They sense an opportunity to enter the

advanced packaging business via fan-out

technology. These players include those

who missed the early FOWLP wave

with eWLB technology. For example,

PTI, ASE , SEMCO and Un imicron

were affected by losses in the substrate

business of more than $100M each year.

Therefore, they want a new business

model that utilizes their experience in

substrate manufacturing. Other potential

entrants include companies that already

have experience in panel processes, for

example, liquid crystal display (LCD)

packaging, and believe they can leverage

this for PLP, like nepes, or those that

want to develop high-density, low-cost

packaging to support their front-end

chip business, like Samsung Electronics

and Intel.

SEMCO i s t he nex t b i g ge s t FO

cont ende r, bei ng pa r t of Samsu ng

Electronics (IDM). Samsung has been

instrumental in design, memory, logic,

packaging, chipset assembly and end-

p r oduc t a nd c a n , t he r efo r e , d r ive

breakthroughs internally. SEMCO, being

part of the Samsung group, is pressured

to develop differentiated yet cost-effective

technology. In 2018, SEMCO achieved a

new milestone by rolling out AP+PMIC

devices with FO embedded panel-level

packaging (ePLP) PoP technology for the

Samsung Galaxy Watch. SEMCO will

continue to innovate for a cost-effective

HDFO market space in order to compete

with TSMC for Apple’s packaging and

FE business again. In years to come,

SEMCO’s HDFO is expected to be

utilized first in Samsung’s smartphones.

Besides, a reorgan i zat ion between

SEMCO and Samsung Electronics could

be beneficial for Samsung’s position as a

full turnkey provider for a FE+BE bundle.

This will be a direct battle against TSMC

fighting to be the supplier for Apple’s APE

die and packaging business.

Currently, PTI has successfully secured

MediaTek’s business in automotive radar

applications. Qualcomm and MediaTek

will continue to request mid-end to high-

end devices at lower price from OSATS.

Wit h new mega-t rend appl icat ions

requesting more f unctionalities and

shorter routings, a larger package with

multi-dies like processor+memory is

ideal. PTI is a good choice for fabless/

IDMs/foundries because PTI is already

a specialist in memory packaging and a

driver in FOPLP. PTI is investing $1.6B

in a new FOPLP fab and we can expect

PTI to emerge as a cost-effective leader

in FOPLP technology for core FO in the

years to come.

Summary

It can be concluded that opinions are

still divided, and strategies are different

in this new age digital era. Clearly, fan-

out packaging is growing strongly in a

landscape that is more fragmented than

ever. Consequently, different levels of

battles are unfolding in both the core FO

market and the HDFO market.

References

1. Fan-Out Packaging: Technologies

and Market Trends report, Yole

Développement, 2019.

2. Fan Out Panel Level Packaging

(FOPLP): Samsung is playing a

strategic game – An interview of

SEMCO by Yole Développement,

published on

i-micronews.com

3. S. Elisabeth, S. Kumar, “FOPLP

vs. FOWLP: the battle between two

giants, Samsung and TSMC,” 2018.

Biographies

Favier Shoo is a Technology and Market Analyst in the Semiconductor & Software division at Yole

Développement (Yole), member of Yole Group of Companies. Based in Singapore, he is engaged in the development

of reports as well as the production of custom consulting projects. With prior experience at Applied Materials and

REC Solar, he developed a deep understanding of the supply chain and core business values. Being knowledgeable

in this field, Favier has conducted professional training for industry players and obtained two patents. He was also

the co-founder of a startup company. He holds a Bachelor’s degree in Materials Engineering (Hons) and a minor in

Entrepreneurship from Nanyang Technological U. (NTU), Singapore. Email:

shoo@yole.fr

Santosh Kumar is a Principal Analyst and Director Packaging, Assembly & Substrates, Yole Korea, a member company of

Yole Développement (Yole). Based in Seoul, Santosh is deeply involved in the market, technology and strategic analyses of the

microelectronic assembly and packaging technologies and presents his vision of the industry in numerous conferences, as well as

through papers and patent publications. His main interest areas are advanced IC packaging technology including equipment and

materials. He is the author of several reports on fan-out/fan-in WLP, flip-chip, and 3D/2.5D packaging. Santosh Kumar received

Bachelor’s and Master’s degrees in Engineering from the Indian Institute of Technology (IIT), Roorkee, and U. of Seoul, respectively.