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20

Chip Scale Review July • August • 2019

[ChipScaleReview.com]

Advanced packaging carriers for WLFO applications

By Jay Zhang, Yu Xiao, Andy Teng, Indrajit Dutta, Varun Singh

[Precision Glass Solutions, Corning Incorporated]

and Lei Yang, Ming Li

[ASMPT]

an-out wafer-level packaging

(FOWLP) has been around

f o r m a n y y e a r s w i t h

embedded wafer-level ball grid array

(eWLB) being the most well-known

solution in the industry. Applications

of FOWLP reached a new phase i n

2016 when TSMC’s integrated fan-out

(InFO) platform was commercialized to

address application processor (AP) uses

in a mobile phone. For such higher-end

applications, a glass carrier becomes

the preferred choice during the FOWLP

process for the following reasons:

• Glass can deliver a wide range

of precise coefficients of thermal

e x p a n s i o n ( C T E s ) i n f i n e

granularity to match different fan-

out (FO) ratio and epoxy molding

compound (EMC) properties.

• Glass enables st ress-f ree laser

debonding;

• Glass wafers can deliver very low

total thickness variation (TTV);

• I n some ca s e s , g l a s s of fe r s a

ver y smooth surface to deposit

f ine redistribution layer (RDL)

features; and

• Glass can often be reused multiple

times.

As t h e i nd u s t r y ma t u r e s , mo r e

sophisticated packaging structures are

being considered, and the FO process

is also becoming more complex. In

many high-end applications, yield is

key to product and business success,

and a high-yield process often demands

new and improved materials to deliver

superior performances. Warp control is

key in any FO applications, and a glass

carrier plays a critical role in managing

warp throughout the FO process.

Why i s wa r p s o i mpo r t a n t i n a

t ypical FO process? Wa r p impact s

how a wafe r behave s wit h va r ious

process tools. For example, spin coating

and EMC backgrinding both rely on

vacuum chucking for proper operation.

Va cuum chuck i ng de pend s on t he

wafer being sufficiently f lat. Another

example is physical vapor deposition

(PVD), such as metal adhesion layer

and Cu seed layer deposition using

s pu t t e r i ng . I n t he s e c a s e s , wa fe r

f latness ensures proper heat sinking,

and thereby film thickness and property

uniformit y. Some lithography steps

also require that the top su r face is

f lat within the depth of focus of the

lithography system, and bad warp could

lead to improper feat u re def inition

and development. A rule of thumb is

that throughout the FO process, being

able to control warp to be <1mm is a

good practice [1].

Levers to control warp

We begin by f irst developing the

f undament al underst anding of how

FO processes generate warp. To model

warp, we consider a typical FO structure

as a bi-layer in which the bottom is

the glass carrier, typically 0.5-1.2mm

in thickness. The top of the structure

is a combination of

ma t e r i a l s t h a t a r e

a d d e d a s t h e F O

process prog resses.

Fo r e x a mp l e , i n a

t y p i c a l c h i p - f i r s t

s c e n a r i o , d i e s a r e

placed on an adhesive

f i l m , f o l l owe d b y

EMC molding, EMC

backgrinding, RDLs,

and finally, bumping.

At any process step,

we ca n pic t u r e t he

added composite layer

as a single layer with

an average proper ty

of t he con s t it ut i ng

materials. As shown

i n

F i gure 1

, let u s

call that a semiconductor layer and use

subscript

s

to designate the material

properties of this layer, E

s

for Young’s

modulus, t

s

for the layer thickness, υ

s

for Poisson’s ratio, and α

s

for thermal

expansion coefficient. For the carrier

glass, we use subscript

g

for the same

parameters accordingly.

Assuming the bi-layer is fabricated

with no stress at process temperature

o f

T

a n d t h e n r e t u r n s t o r o o m

temperature, and we further assume

that CTE mismatch is the dominant

s t r e s s - p r odu c i ng me ch a n i sm , t he

resulting warp in the simplest form is

expressed as:

It is clear that ΔCTE and ΔT are

both linear in contributing to war p.

If CTE can be perfectly matched, or

t he fabr icat ion proce ss is at room

t empe r at u r e, we shou ld expe ct no

warp. In reality, the FO process adds

F

Figure 1:

Model of warpage in a typical fan-out structure.

Eq. 1