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Chip Scale Review July • August • 2019

[ChipScaleReview.com]

Reliability physics analysis (RPA) of semiconductor packaging

By Gil Sharon, Nathan Blattau, Maxim Serebreni, Greg Caswell

[ANSYS]

he use of simulation tools to

model the performance of

semiconductor packagi ng

is a well-known practice. However,

because of resource limitations and prior

experience, these activities are typically

highly limited to key product lines and

generic environments. With the explosion

in package geometries to meet the unique

demands of electrification, autonomous,

and internet of things (IoT) market drivers,

semiconductor manufacturers are being

challenged to quantitatively understand these

variations and how reliability may change in

a customer-specific application. This paper

will discuss how reliability physics analysis

(RPA) is increasingly being used by the

semiconductor industry and its customers

to understand package-level and board-level

reliability (BLR) and to clearly communicate

performance expectations during material

selection and product design. RPA is a

technique that leverages the philosophy of

physics of failure and simulation to predict

mechanism-specific reliability performance.

Identifying oppor tunities for model

simplification based on industry standard

geometries and implementing closed-form

equations to replace time-stepping analyses,

RPA allows for more agile evaluation of

design and material options and provides

insight into system-level effects on package-

level reliability. Two key case studies that

demonstrate the capability of RPA to

improve the design and qualification process

of semiconductor packaging, solder fatigue

and low-k cracking, are reviewed.

Introduction

The silicon-based transistor gate is the

fundamental enabling technology that

drives innovation. The transistors on the

silicon needs to be connected to the rest

of the world through the package. The

size and scale of the connection between

the silicon die and the package makes it

difficult to directly measure the stresses

in the package. There have been many

advancements in simulation capabilities

regarding package design. This paper

discusses how RPA is increasingly being

used by the semiconductor industry and

its customers to understand package-level

reliability and to clearly communicate

performance expectations during material

selection and product design.

The fundamental properties

of silicon

T he s i l i c on d i e p r o c e s s i ng a nd

manufacturing process begins with wafers.

Wafers are round discs of single crystal

silicon that is ready for deposition of

materials that will make the individual gates

and interconnects of the individual “chips.”

Each silicon wafer is processed as one unit.

A single wafer may contain as many die

as will fit on it. The active layers are the

smallest material structures that create the

gates. These layers, commonly called the

front end of line (FEOL), are highlighted

in red in

Figure 1

. It is common for dies

to have several metal interconnect layers

between gates. The last interconnect layers

also include the I/O aluminum pads. These

layers are commonly called the back end of

line (BEOL) as shown in

Figure 1

.

Many of the problems that are tackled

in semiconductor packaging arise from the

fundamental material properties of silicon.

The coefficient of thermal expansion (CTE)

of silicon is 2.6ppm/°C and the elastic

modulus is 130GPa. The active layers are

made from materials that have a different

CTE than silicon.

As shown in[2]

Figure 2

, the CTE

mismatch between the active layers and the

silicon material can cause the wafer to warp.

The die warpage can be predicted with finite

element modeling (FEM) techniques. The

stress in the die can influence chip-package-

interaction if the stress in the die and active

layers is high enough. The stresses will

remain even after the individual die are

singulated. Die warpage is an indicator

T

Figure 1:

Cross section examples of the FEOL and BEOL structures on a silicon die. The FEOL structure is

highlighted in red [1].

Figure 2:

Example of a wafer warpage caused by CTE mismatch between the active layers and the silicon wafer [2].