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Chip Scale Review July • August • 2019



July • August 2019

Volume 23, Number 4

Data centers (i.e., AI, machine learning,

deep learning, computation run-off

data center hardware) are driving next-

generation semiconductor packaging,

especially 2.5D and 3D integrations. In

particular, data centers are the primary

target market for 3D DRAM, 3D NAND for

SSDs, and 2.5D CPU/GPU/FPGA/SoCs,

etc. These devices are the focus of all the

large semiconductor companies for not

only their current high-end product lines,

but also those of the future.

Cover art courtesy: XPERI Corporation

16 27 31 35 40 The battlefields of fan-out packaging Favier Shoo, Santosh Kumar Yole Développement Reliability physics analysis (RPA) of semiconductor packaging Gil Sharon, Nathan Blattau, Maxim Serebreni, Greg Caswell ANSYS MRAM testing for high-volume manufacturing Siamak Salimy Hprobe MEMS packaging trends: from LGA to 3D integration Stéphane Elisabeth, Audrey Lahrach System Plus Consulting Surfaces matter for semiconductors Edward Hughes, Don Cunningham Aculon, Inc. Industry News


45 Guest Editorial 8 Improving 2.5D packaging design flow: a brief history Tony Mastroianni eSilicon Corporation Technology Trends 5 Semiconductor-on-Polymer™chip-scale packaging (SoP CSP) Douglas Hackler, Dale Wilson American Semiconductor Edward Prack MASIP LLC 10 Enabling the new 3D architecture Javier DeLaCruz XPERI Corporation 20 Advanced packaging carriers for WLFO applications Jay Zhang, Yu Xiao, Andy Teng, Indrajit Dutta, Varun Singh Precision Glass Solutions, Corning Incorporated Lei Yang, Ming Li ASMPT