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Chip Scale Review July • August • 2019

[ChipScaleReview.com]

MRAM testing for high-volume manufacturing

By Siamak Salimy

[Hprobe]

ndustry interest in perpendicular

spin transfer torque magnetic

random access memory (STT-

MRAM) technology as a new nonvolatile

memory (NVM) has been confirmed by

the production schedules of major foundries

announced last year. Today, the technology

is considered as one of the most promising

emerging NVM devices for embedded

applications. Thanks to its fast writing speed,

lower power consumption, and the ultra-low

latency of STT-MRAM, several applications

are targeted such as static random access

memory (SRAM) replacement in last-

level cache (LLC), dynamic random

access memory (DRAM) replacement in

data centers, and memory control units

(MCU) for artificial intelligence (AI) and

neuromorphic calculation.

MRAM technology scalability down to

low single-digit technological nodes has

been an important driver for big industrial

players implementing their Moore’s law

journey. Shrinking of the unit memory

cell (i.e., the magnetic tunnel junction)

below 10nm was demonstrated last year

by research groups from Spintec [1] and

Tohoku University [2]. Performance and size

shrinking drivers resulted in consequential

efforts with large investments to transfer

STT-MRAM technology to the back end of

line (BEOL) of the 300mm manufacturing

process for embedded memory applications.

Samsung and GLOBALFOUNDRIES will

offer STT-MRAM embedded in the fully-

depleted silicon on insulator (FD-SOI)

process at 28nm and 22nm, respectively.

Taiwan Semiconductor Manufacturing

Company (TSMC) will start producing in

28nm, as well as United Microelectronics

Company (UMC). Lastly, Intel announced

the manufacturing of MRAMmemory chips

in its 22nm FinFET process.

STT-MRAM

STT-MRAM is based on a perpendicular

magnetic tunnel junction (pMTJ) build

with a stack of thin-film layers including a

minimum of two magnetic films, fixed and

free layers, with a thin insulator between

them. Each magnetic layer has its intrinsic

electronic spin oriented in the up or down

direction as illustrated in

Figure 1

. If the

two magnetic orientations are parallel, the

MTJ is in the lower resistance state (bit ‘0’).

If the two orientations are in the opposite

direction, the resistance is in high state (bit

‘1’). Applying an external field perpendicular

to the device surface can switch it from one

state of resistance to another as shown in

the hysteresis cycle (

Figure 1

). Switching

can also be done by STT using an electronic

current passing through the MTJ. One MTJ

associated with one transistor builds a single

bit memory cell that when duplicated “n”

times in a matrix array creates the number

of bytes required by the application. The

MRAM manufacturing process has most

steps in common with a traditional BEOL

CMOS process with the exception of the

MTJ formation step, where the device is

placed in between the M(i) and M(i+1)

metallization layers.

Challenges in MRAM testing

The specificity of STT-MRAM in being a

magnetic memory based on a perpendicular

magnetic tunnel junction requires that the

MRAM wafers be tested using an external

perpendicular magnetic field while doing

electrical probing. In addition, the probing

is done with high-frequency hardware that

provides the ultra-narrow time domain

voltage/current pulses used to write and read

the devices. The use of a varying external

magnetic field above the wafer while

probing brings some difficulties, which

includes having a fast sweeping capability

for time domain pulsing. Both of these

requirements are difficult to integrate into a

300mm wafer probing system. Furthermore,

electrically probing wafers with STT-

MRAM under a magnetic field with testing

time performances compatible with volume

manufacturing requirements is challenging.

Test requirements for STT-MRAM.

The test requirements for STT-MRAM, the

wafer-level testing is done by:

1. Applying a variable magnetic field in

the perpendicular direction above the

device for extraction of the hysteresis

curve as illustrated in

Figure 1

. This

is done to evaluate the ability of the

unit cell to switch from one state

to another and to extract physical

parameters giving insight on the ability

of the memory cell to retain the stored

I

Figure 1:

Illustration of a perpendicular magnetic tunnel junction and its resistance vs. perpendicular

hysteresis cycles.