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Chip Scale Review July • August • 2019


Surfaces matter for semiconductors

By Edward Hughes, Don Cunningham

[Aculon, Inc.]

he demand for innovation

across the semiconductor

industry is accelerating. As the

demand grows, system original equipment

manufacturers (OEMs) are fueling the

drive toward ever higher performance

features, higher speed data transmission,

higher definition video, effortless data

access, and power storage in smaller,

smarter, faster, thinner electronic devices.

The race for miniaturization and the

development of chips with transistor

a nd f u nc t ion den sit ie s p r ev iou sly

unimaginable requires immediate access

to new mater ials that can be easily

applied and manipulated. Chip designers

and manufacturers are responding with

new packaging concepts with mandates

to squeeze as much as possible from

existing packaging design rules. The

new semiconductor product design

elements are the instigators of diverse

new package form factors/outlines; new

production formats driven by production

cost reductions; and the slowing of

Moore’s Law. The new product concepts,

structures, and formats are challenging

and exceeding the limits of industry-

standard materials.

Nanoscale surface treatments

Newly developed nanoscale surface

treatments and previously developed

su r face t reatments re-pu r posed for

semiconductor package surfaces with

proper ties that enhance and extend

the functionality and performance of

existing base materials are meeting

those challenges. Just as alloying metals

achieves elevated performance with base

elements, new surface treatments can make

base elements, such as copper and silver,

perform new or more expanded functions.

They protect tiny surfaces, provide more

structure for design rule freedom, narrow

process variation of other materials, reduce

production costs, extend the useful life of

existing materials, enable use of lower cost

materials, and increase the wear-life of

high-volume equipment components.

Die attach in the package assembly

environment is a particularly delicate

step in the manufact u r ing process.

Continuously escalating performance

requirements only add to the challenge.

Bonding a super thin, large area flip-chip

onto a laminate substrate or a tiny chip

on a wire bond metal lead frame stretches

the processes that use epoxy, soft solder,

eutectic and flip chip. Each combination

presents unique challenges in both the

process and the execution. Integrating

surface treatments into the processes

mitigates several of these challenges while

enhancing performance.

Among the new approaches noted

above are technologies available today

that generate highly ordered nano-scale

films called self-assembled monolayers

(SAMs), which feature an unprecedented

mechanism for adhering to a wide variety

of metals including precious metals that

are normally unconsidered unreactive

such as gold and silver, and creating a

high-performance repellent surface to

control the location of high adhesion

materials. These SAMs are nano-scale

self-leveling materials, which allow

great freedom with low-cost application

methods such as selective spraying,

dipping, or wiping. Thicknesses of

different versions of SAM’s range from

2nm to 20nm are shown in

Figure 1

. The

self-assembling nature allows a small

variation in thickness for each version for

significant performance predictability.

Because of their nanoscopic scale, SAM-

enabled treatments have no impact on

electrical or thermal resistance, thereby

imparting valuable functionality without

negatively impacting performance. In

addition to repellency, SAMs can be tuned

chemically to impart adhesion promotion.

T h e s em i c ond u c t o r i nd u s t r y i s

continually searching for die bonding

materials that take up less package area

outside of the die-to-epoxy-to-substrate

interface while exhibiting high adhesion

t o prevent delami nat ion. An ideal

material would also do the following: 1)

offer excellent thermal conductivity to

dissipate the heat generated from the die;

2) develop perfect contact between the

chip and substrate without any voids; 3)

be low stress to maintain silicon integrity;

and 4) be able to withstand extreme

temperatures without degradation. SAM-

based nanocoating surface treatments,

sometimes one-to-four nanometers thick,

meet these criteria. They enable superior

control of epoxy and solder location in

semiconductor packaging, particularly

in flip-chip, lead frame, and stacked-die

packages. Die attach epoxy, epoxy mold


Figure 1:

Epoxy repellent coating 2-20nm thickness.