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Chip Scale Review March • April • 2017


One example of a direct feedback loop

is using the EVG


40NT metrology tool

for alignment verification in combination

with the SmartView


bond aligner.

The requirement for the alignment in

this case is ±100nm, which requires a

measurement accuracy of 10nm. With the

feedback loop from the metrology tool

to the aligner, it is possible to achieve

significant alignment improvement

within five wafers (

Figure 2


Another example for this type of

feedback loop is spin coating parameter

optimization. Some coating materials

change their viscosity slowly over time on

account of solvent evaporation and other

factors. If this solvent evaporation can’t be

prevented, metrology can help to achieve

reproducible coating thicknesses. The

thickness of the coated wafers is measured

High-accuracy metrology for advanced

packaging applications

By Elisabeth Brandl, Markus Heilig, Thomas Uhrmann, Thomas Wagenleitner

[EV Group]

he semiconductor industry is witnessing a

trend toward total control and monitoring of

all production processes. Mid-end-of-line

(MEOL) and back-end packaging processes face tighter

process constraints at levels previously seen only in front-

end-of-line (FEOL) wafer processing. With every process

step there is a risk of error, affecting the whole wafer or

individual dies on it. This is creating an urgent need for

highly accurate metrology both in stand-alone equipment as

well as integrated into process equipment that can provide

critical process data quickly and cost-effectively.

For example, before nonreworkable processes, such as

wafer thinning after temporary bonding, high-accuracy

metrology with a feedback loop leads to an increase

in yield through more accurate thinning and process

optimization decisions. In this case, non-destructive and

high-throughput infrared (IR) metrology integrated into

process equipment is ideal for permanent and temporary

bonding applications as it offers thickness measurements,

verification of homogenous bond lines and void detection.

For chip or wafer stacking, as well as for lithography

applications, alignment verification implemented in

stand-alone equipment is useful in generating correction

parameters for the alignment process itself.

Process control

Metrology tools can be versatile and enable inspection

both before and after a given process. Therefore, the

influence of a given process on the overall production flow

can be determined, which leads to a greater understanding

of the process and allows improved process control accordingly. Process control is a

key criterion for reproducibility, especially for high-volume manufacturing (HVM).

For bonding and lithography in advanced packaging, wafer alignment and thickness

uniformity are critical parameters in the production line. Optical inspection methods

offer high accuracy and wide measurement range by employing different wavelengths,

making it a suitable measurement method for alignment verification and thickness

measurements. To enable sufficient verification, the measurement accuracy must be

ten times better than the needed accuracy of the parameter. As an example, verification

of 100nm alignment accuracy requires a measurement accuracy of 10nm.

Direct feedback loop for process parameter optimization

Process parameter optimization, like alignment improvement, is an effective way to

enhance the yield in production lines and can be realized with a direct feedback loop


Figure 1

). Metrology consisting of a suitable inspection and analysis is done after the

production process step. Correction factors are calculated from the metrology output,

which improve the process for subsequent wafers. With this method, the process

parameters are constantly improved, which leads to an optimized process. This

feedback loop is limited by the metrology accuracy and the precision of the process

parameter adjustment.


Figure 1:

Direct feedback loop for process parameter optimization.

Figure 2:

Integrating a direct feedback loop leads to significant alignment improvement

within 5 wafers.