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14

Chip Scale Review March • April • 2017

[ChipScaleReview.com]

NCP from between the bump's solder caps and

the substrate pads, and, furthermore, slightly

deforms the bumps to establish good thermal

die-substrate contact. In parallel, a temperature

profile is applied in order to melt the solder

and to cure the NCP.

Initially, the NCP is cured sufficiently

before solder reflow, allowing the NCP to

provide a sufficient reaction force to prevent

a sudden collapse of the die once the solder

cap melts. After a certain dwell time, the

solder melts and forms the joint to the pad on

the substrate side, while the NCP continues

to cure completely. At this point, the bond is

complete and the bond tool can immediately

release the die, cooling down in parallel while

fetching and aligning the next die. Throughout

the process, the stage heating is controlled to

maintain it always at a constant temperature.

Keeping these few principles in mind, the

bond control for TC-NCP is quite simple. The

selection of NCP is critical for the achievement

of a reliable interconnect [3]. With long-term

availability of suitable NCP materials (more

than 6 years), the TC-NCP process is robustly

applicable in many areas.

For ultra-thin (e.g., 20-50µm) die, however,

the NCP bleed-out is very hard to control

in order to avoid NCP

climbing up the die edges

and contaminating the bond

tool. This is essentially the

reason why TC-NCP has

not been considered for

3D memory production,

besides the lack of available

NCP that is compatible

with extra low-k (ELK)

dielectrics used in advanced

CMOS nodes.

These drawbacks of TC-

NCP were the main reason

why thermocompression

capillary underfill (TC-

CUF) has been introduced

for high-volume TCB

production (

Figure 1b

). With the TC-CUF

process, CUF is applied downstream from

the TC bonding step, therefore, no underfill

is present during bonding. In most cases,

flux dipping is applied after die flip, although

other methods such as upstream spray fluxing

onto the substrate also exist. After the die is

dipped in flux, it is bonded onto the substrate

again with the use of force and temperature

profiles. The absence of underfill during

solder reflow comes with serious challenges

for bond control, which will be explained

later in detail. It is worth mentioning that TC-

CUF is the most widely deployed TC bonding

process on the market with an estimated 200

TC bond heads running TC-CUF for high-

volume manufacturing of hybrid memory

cubes and computing/server logic.

The application space for TC-CUF is

considerably wider than that for TC-NCP. TC-

CUF is capable of memory cube production,

and compatible CUF materials are readily

available at high maturity levels. However,

TC-CUF has one big disadvantage: it cannot

be used as a basis for collective TC bonding

processes, which promise a TC bonding cost

reduction by a factor of five [4].

The requirements for collective TC

bonding are supported by a nonconductive

film (TC-NCF) (

Figure 1c

). In this process,

a non-conductive film-based underfill

(NCF, sometimes called WLUF, i.e., wafer-

level underfill) is applied at wafer level [5].

The basic process runs similar to TC-NCP,

although underfill is present on the die side

rather than on the substrate side. This means

that the NCF is directly exposed to the TC

bonder tool temperature, and therefore, die

Core capabilities of a thermocompression bonder

By Hugo Pristauz, Alastair Attard, Andreas Mayr

[Besi Austria GmbH]

hermocompression bonding

(TCB) is now a well-established

interconnection technology for

2.5D- and 3D-integrated devices that are built

on chip-to-substrate (C2S), chip-to-chip (C2C),

or chip-to-wafer (C2W) levels. The maturity

of TCB has progressed over recent years, with

yield levels greater than 99.8% per attached

die. Though industrial interconnect pitches

are still found above the 30µm level, the new

paradigms of heterogeneous integration are

driving pitches down to 5µm for stacked ICs

(SICs) and down to 1µm for system-on-chip

(SoC) devices. In order to leverage TCB for

such advanced interconnection pitches, it is

essential to understand the core capabilities

of a TCB, which directly contributes to the

required high-yield levels. In particular, the

complexity of these core capabilities need to

be well understood in order to further improve

them for high-yield bonding of 2.5D and 3D

devices with scaled pitch.

Today, 2.5D and 3D integrated stacked

ICs (SICs) are widely adopted, with the

main applications being high-performance

computing, graphics processors and 3D

through-silicon via (TSV) memory [1]. In

the case of 3D system-on-chip (SoC) large

volumes have been driven in the image sensor

area for camera applications [2]. In contrast

to 3D-SoCs, where the interconnection is

achieved by wafer-to-wafer (W2W) bonding,

the assembly of 3D-SICs utilizes C2S, C2C

and C2W methods, mostly based on TCB,

which enjoys advantages such as known-good-

die (KGD) yield benefits as well as enabling

greater heterogeneous integration.

TCB process flows

Three process variants of TC bonding have

been established for high-volume production.

Thermocompression nonconductive paste

bonding (TC-NCP) (

Figure 1a

) is the pioneer

of TC bonding [3]. The TC bonder receives

a substrate with pre-applied underfill (i.e.,

the nonconductive paste) that is dispensed

upstream of the TC process. The TC bonder

picks and flips a die and, after alignment,

presses the die into the paste. At this point, the

actual thermocompression phase starts. A force

ramp is applied in order to squeeze out the

T

Figure 1:

Different TCB process flows.