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Chip Scale Review March • April • 2017

[ChipScaleReview.com]

mbedding and fan-out are two

different technologies, but

they can be combined into

one at either wafer-level, panel- or board-

level. All the packaging technologies can

be classified into four types as shown in

Figure 1

: a) wafer-level packaging, b)

embedded packaging, c) fan-out packaging,

and d) embedded and fan-out packaging.

Embedding and fan-out technologies

Wafer-based packaging is emerging

as a strategic and dominant packaging

technology because of its many benefits.

It started as a wafer-level packaging

technology by simply redistributing the

back-end-of-line (BEOL) wiring on wafers

in the wafer fab and placing solder bumps

on the entire wafer, and then singulating the

packaged ICs, ready for board assembly.

This WLP is a single unit with a continuum

of interconnections from transistors to

BEOL, to redistribution layer (RDL), and

to solder bumps. All WLPs are chip-scale

packages with chip and package sizes

nearly the same. This is the best package

electrically. But it is limited to small ICs

and to small packages, typically below

5mm. As such, it is limited in external

I/Os to connect to the board, typically at

400 microns in pitch.

To eliminate the board-level I/O limitation

of WLPs, wafer fan-out technology was

developed. The fan-out means fanning out

of I/Os beyond the footprint of the IC in the

package. Fan-out technology, by itself, is not

new; in fact, most of the billions of packages

since the 1970s are manufactured annually

as fan-out packages.

Figure 1c

, a ball grid

array (BGA) package – one of the more

recent packages – is an example of a fan-out

package. These are manufactured, however,

not as round wafers in the wafer fabs, but

as strips, panels or boards, in package

and board foundries. The “embedding”

technology, as shown in

Figure 1b

, began to

emerge as another paradigm in packaging.

In this technology, RDL wiring is directly

deposited on reconstituted ICs into 200 or

300mm round wafers by molding them

with epoxy-based molding compounds.

Embedding means the chip is embedded

or buried inside the package or board and

the interconnections are made to and from

these buried ICs using either wafer BEOL

tools or package tools. The new trend,

often referred to as wafer fan-out (WFO),

includes both of these technologies at wafer-

level. It should really be called embedded

wafer fan-out (eWFO) as is done in this

article. Such a concept of a combined fan-

out and embedding, as shown in

Figure

1d

was originally developed in the 1980s

by GE for military applications, and then

followed by many others including Intel as

bumpless build-up-layer (BBUL), Freescale

as redistributed chip packaging (RCP), and

more recently, further developed by Infineon

as embedded wafer-level packaging

(e-WLP), and manufactured by STATS

ChipPAC, NANIUM S.A., and others.

eWFO technology, however, is not

wafer-level packaging, as described above.

It is packaging of singulated ICs that are

reconstituted back into 300mm wafers

and addressing the I/O limitation of WLPs

at board level. It is also an embedded

packaging technology with more benefits

than simply fan-out, such as reduced

package thickness, and not requiring

assembly because the wiring is deposited

directly on the surface bond pads of ICs.

It has high I/O density at chip level, the

shortest interconnections between IC and the

RDL wiring, and is an ultra-thin package.

eWFO, however, has many challenges in

applying it to next-generation needs, as

summarized below:

• Die placement accuracy, die shift and

die pad coplanarity;

• Molding compound shrinkage and

wafer warpage due to molding

compounds;

– Limited RDL scaling in contrast to

the potential of BEOL scaling and

pitch;

– High electrical loss of EMC and

RDL dielectric loss;

• Outgassing of RDL polymers during

sputtering;

• Board-level reliability;

– Limited to small-to-medium size

ICs and packages;

– Difficulty in IC removal and

repairability of high-value single

chips or multi-chips; and

– High cost for large size packages

beyond 20mm in size.

The concepts of embedding and fan-

out have many applications, as described

below. All applications benefit from

embedd i ng wh i l e f an - ou t bene f i t s

mostly higher I/O applications such as

packaging of processors and other logic

devices. Independent of eWFO, panel-

and board-based embedding is emerging

as a very high throughput and lower

cost technology that is bound to move

up to higher I/O fan-out capabilities, as

described in this article.

E

Future of embedding and fan-out technologies

By Rao R. Tummala, Venky Sundaram, P.M. Raj, Vanessa Smet, Tailong Shi

[Georgia Institute of Technology]

This paper was originally published in the proceedings of the SMTA Pan Pacific Microelectronics Symposium, Kauai, Hawaii, February 6-9, 2017.

Figure 1:

Four types of packages: a) wafer-level

package (WLP); b) embedded package; c) fan-out

package; and d) embedded and fan-out package.