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Chip Scale Review March • April • 2017


machine failures are

a few examples of

special causes that

c an c au s e de f e c t s

t o b e i n t r o d u c e d

i n t o s ome o f t h e

manufactured units.

2. Parametric: Many

t e rms a r e u s ed t o

describe these failures,

but it all comes down to

cases where the desired

product characteristics

cannot be consistently

a c h i e v e d w i t h

t h e a v a i l a b l e

manufacturing process.

The part will generally

function correctly, but

will not meet some

expected performance

characteristic. These

rejects are caused by

common causes.

C o m m o n c a u s e

(parametric) rejects are a

result of product requirements

(specifications) that are less

than the distribution of the

manufacturing process. Test

engineers will describe this

as a requirement to “truncate

the distribution to meet spec.”

In a normal distribution, if

the specification accepts +/-3

sigma of the manufacturing

distribution, then 0.27%

(2700DPPM) of the product

will be nonconforming. If the specification

accepts +/-6 sigma, then 0.006% (60DPPM)

will be nonconforming.

When test is used to truncate the manufacturing

distribution this way, the result will be that

some nonconforming product will be shipped.

This is a result of the simple fact that all test

measurements have uncertainty (i.e., common

cause measurement variation). Any tested

product parameter that is close to the product

spec limit will have some probability of

resulting in an incorrect pass/fail result for that

parameter on account of test measurement

variability (

Figure 2


The number of reject units shipped is some

fraction of the actual rejects manufactured. The

size of that fraction is related to the measurement

accuracy of the test. For this discussion, it is

sufficient to point out that for parameters with a

+/-6-sigma spec limit, the fraction is multiplied

by a 60DPPM population of nonconforming

units. For products with a +/-3-sigma spec limit,

that same fraction is multiplied by a 2700DPPM

population of nonconforming units. Everything

else being equal, the 3-sigma spec limit

Chip over-test: are ICs tested too much?

By Dale Ohmart

[Texas Instruments]

t can be difficult to understand the

trends of test cost in the IC industry.

One common metric is to measure

the capital spent on test systems against the

revenue produced by chip makers (

Figure 1


When evaluated that way, it appears that there

is a long-term trend in the downward direction.

Over the last five years, this downward trend has

slowed significantly. As the average selling price

of automatic test equipment (ATE) systems has

come down over the last several years, the cost

of handling equipment and infrastructure has

grown to roughly 50% of test cell capital price.

The total capital investment for test is currently

around 2% of semiconductor revenue.

Industry growth over the next few years is

forecast to be in the industrial and automotive

markets. Industrial and automotive applications

generally demand more complex and expensive

test flows. It seems safe to conclude that there

will be upward pressure on test costs over

the next few years. Test professionals should

see this as a challenge. More specifically, the

following issues should be considered: 1) How

can test cost reduction be accelerated?; and 2)

More testing, and consequently higher test cost,

is perceived as a path to better quality (e.g.,

automotive, industrial applications). Is more test

the best way to achieve better quality?

IC manufacturing test and quality

The primary purpose of testing ICs as part

of the manufacturing process is to identify

defective units and remove them from the

population of units delivered to customers. The

test process is required due to the fact that IC

manufacturing produces a mix of units, some

that conform to the product specifications and

some that do not conform. Conforming units

will be called “good” units, and nonconforming

units will be called “rejects.”

I n IC ma nu f a c t u r i ng , r e j e c t s c a n

generally be classified as being produced in

one of two ways.

1. Defects: Defects are inherent in

the IC manufacturing process. The

geometries are very small. There

are a large number of process steps.

Particle defects, setup errors, and


Figure 1:

Capital spent on test systems vs. revenue produced by chip

makers. SOURCES: Gartner, iSuppli

Figure 2:

Four outcomes of 100% inspection.