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Chip Scale Review March • April • 2018


By Ramachandran K. Trichur, Rama Puligadda, Tony D. Flaim

[Brewer Science, Inc.]

Sacrificial laser release materials for RDL-first

fan-out packaging

he semiconductor industry

is in a new age where device

scali ng will not cont i nue

t o p r ov ide t he c o s t r e duc t ion s o r

performance improvements at a similar

rate to past years when Moore’s law

was the guiding principle for integrated

circuit (IC) scaling. The cost of scaling

below 7nm nodes is rising substantially

and requires significant investment in

capital equipment and R&D spending for

next-generation lithography solutions.

The demand for higher performance,

smaller form factor, denser integration,

and lower-cost devices is increasing more

than ever due to significant progress

made in products and services developed

for consumer electronics, mobile devices,

cloud comput i ng, aut omot ive, and

various other applications. While the

semiconductor industry continues to

advance scaling of the integrated circuits,

it is also turning to advanced packaging

technologies to increase performance and

integration while lowering costs.

One of t he several challenges i n

heterogeneous integration is to bridge

the gap in the I/Os available at the die

level and the board level. At the die level,

the trend has always been shrinking

die sizes with increasing I/O density,

so creative packaging technology is

required to connect the dies to the board

at such high I/O densities. Numerous

evolving packaging technologies play

a role in heterogeneous integration of

devices, among which wafer-level fan-out

(WLFO) packaging technology has been

emerging as a dominant process. The

WLFO process has been commercially

deployed for several years with simple

single-die designs, a single redistribution

layer (RDL) on one side of a reconstituted

wafer, and sparse silicon areas on thick

reconstituted wafer profiles that resulted

in thicker packages.

Mo r e r e c e n t l y, t o a d d r e s s t h e

performance, integration, and form factor

demands from the end users, design and

process complexity of fan-out packages

has continued to increase with multi-

die packages, integrated passives, multi-

RDL layers, and also 3D fan-out packages,

while continuously reducing the package

dimensions in the x, y, and z directions. As

die size, process complexity, and package

complexity increase, yield becomes a

critical element of the fan-out packaging

process. The traditional fan-out process

uses a chip-first/RDL-last approach where

a reconstituted wafer is built using known

good dies followed by RDL build up on top

of the reconstituted wafer. As the complexity

of the reconstituted wafer and RDL grows,

this process is susceptible to yield loss at the

RDL level where a known-good die (KGD)

is located in a bad RDL location. The

yield loss could be due to several factors,

including die shift, thermal expansion

mismatch, poor lithography alignment, etc.,

resulting in the loss of an expensive KGD

during the packaging process.

To avoid KGD loss during packaging,

a n a l t e r n a t e f a n - ou t p r o c e s s wa s

developed called RDL-first/chip-last fan-

out packaging. In this process, the RDL

was first built on a carrier wafer and

KGDs were placed on top of a known

good RDL location, thereby avoiding

KGD loss. The RDL-first process also

offers other advantages in terms of

finer line/space dimensions for RDL to

offer complex routing for denser device

integration. In this paper, we present

sacrificial laser release materials that

support the development of RDL-first

fan-out packaging by addressing some of

the critical challenges encountered during

the process.

FOWLP technology

A s me n t i o n e d a b o v e , t h e f a n -

out wafer-level packaging (FOWLP)

t ech nology broad ly ha s t wo major

process categories (discussed below):

1) chip-first/RDL-last fan-out, and 2)

RDL-first/chip-last fan-out. Advanced

i nteg rat ion schemes i n bot h of t he

p r oce s s r out e s r equ i r e some for m

of ca r r ier-assisted process usi ng a

temporary bonding material.

Chip-first/RDL-last FOWLP.


chip-f irst fan-out process utilizes a

wafer reconstruction process in which

KGDs from the original device wafer

are picked and placed on a substrate

and then over-molded with an epoxy

molding compound and cured to create

a heterogeneous and highly stressed

substrate known as a reconstituted wafer.

If the reconstituted wafers are thinner

than 350µm, these wafers exhibit severe

bow due to large internal stresses, and

a high-temperature-capable temporary

bonding material is essential to support

the reconstit uted wafer through the

process f low [1] to reduce the bow

and to alleviate handling problems in

equipment and registration errors during

alignment for photolithography during

RDL build.

The chip-first process f low has two

generic process routes, reconstituted

wafer handling and build-up process

and hand l i ng.

Fi gure 1

shows t he

general schematic process for both of

these process routes. The predominant

differences in both of these routes occur

during the reconstituted wafer building.

I n process route A – reconst it uted

wafer handling – the wafer is built on

a separate carrier and then transferred

to a second carrier coated with a high-

temperature temporary bonding material

and a release layer for subsequent RDL-

build up and assembly. In process route

B, the chip attach, reconstitution, RDL-

build, and assembly processes happen

on a single carrier coated with a high-

temperat u re - compat ible tempora r y

bonding material and a release layer.

T h e p r i n c i p a l c h a l l e ng e s f o r a

temporary bonding material used for a

chip-first type process include warpage

control, die shift, temperature stability,

etc., and these were add ressed in a

previous publication [2]. The chip-first