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Chip Scale Review March • April • 2018


By Christian Ohde, Henning Hübner, Mustafa Özkök, Ralph Zoberbier, James Welsh

[Atotech Deutschland GmbH]

Extending plating performance to enable FOPLP

his paper describes first results

of a newly developed plating

tool t hat also uses newly

developed electrolytes in order to plate Cu

pillars at high current densities and finer

lines and spaces on large panels (similar

to wafers). These abilities are important

in order to transfer wafer-level packaging

technologies on larger substrate panels

enabling lower manufacturing cost and

increased productivity.

Fan-out wafer-level packaging (FOWLP)

was introduced many years ago and is

now seen as a key advanced packaging

platform to meet the technological and cost

requirements of the industry. Substrate

sizes have increased over the past several

years and now substrates larger than

300mm are poised to take advantage of

the economies of scale in manufacturing

processes. This situation currently drives

the industry and the supply chain, i.e., the

transfer of FOWLP to fan-out panel-level

packaging (FOPLP) and the development

of new products and solutions. The move

from round to square substrates allows

even more dies to be produced in order

to further reduce costs. Though this

transfer offers new possibilities, it also

raises challenges.

A plating tool for panel sizes up to

650×600mm was developed and installed

for detailed investigations. This paper

describes the use of newly developed

electrolytes for high-speed Cu deposition

in RDL layer plating with and without

microvias, as well as tall pillar plating

(package-on-package [PoP] design). The

key requirements for both applications

are uniformity, feature shape, and process

stability. This ar ticle will show the

improvements achieved for each of the

above mentioned requirements during

the past two years. Our investigation

during that time shows that FOPLP has

the potential to be strong competition

for WLP for the coming years. But the

standardization of panel format is seen as

a must in order to achieve the cost-saving

potential promised by this technology.


FOWLP had been introduced to the

market many years ago as a breakthrough

pa ckag i ng t ech nolog y t o meet t he

challenges and demands for thinner

and smaller electrical devices such as

smar tphones, combined with higher

performance and a higher level of system

integration. Since its introduction, the

technology has matured for single-chip

packaging applications and is mainly

used for communication products like RF,

baseband, and Bluetooth packages. Over

the years, many new fan-out platforms

have been introduced with constantly

increasing complexity such as through-

mold interconnections and multiple

RDL layers to ready the technology for

additional and more complex products

and applications like application processor

packaging. Development of the equipment

and materials supply chain tends to focus

on technological improvements and new

solutions to overcome immediate key

issues such as severe wafer warpage, die

shift, and process reliability.

A key differentiator of this technology

is the creation of a new artificial substrate

based on known good dies. In theory,

the shape and size of this substrate has

no limitation as opposed to a traditional

300mm Si wafer. This characteristic

offers new possibilities in package design

and offers significant cost reduction

potential as substrate sizes can easily

be enlarged over the traditional 300mm

wafer format. Many recent publications

a r e d i s cu s si ng t he impa c t on cost

reduction while moving from wafer- to

panel-size substrates. In general, the size

of the manufacturing substrate is a key

driver for the overall cost of the package.

However, it has to be considered that the

biggest savings will only come from

batch activities. While investigating the

cost structure of a fan-out package, RDL

creation is considered to have the largest

impact by approximately 40% of the

overall costs [1]. The largest portions of

the RDL cost itself are the material cost

(e.g., photo-dielectrics and plated Cu) and

equipment related costs for patterning

and metallization. While material costs

are considered to remain on a similar

level, equipment costs per package

directly relate to the number of packages

per substrate that can be processed with a

single process step.

The promise of this cost reduction is

currently driving the industry and the

supply chain to develop new products

and solutions that take advantage of

the substrate scaling possibility. The

main challenge is to develop a solution

t h a t ke e p s , o r eve n i mp r ove s t he

technical performance of the process

step manufactured on a much larger

substrate, combined with cost-efficient

equipment solutions that can keep the

output in substrates per hour at a minimal

equipment cost increase per panel.

T h e a c t u a l s u b s t r a t e s i z e w i l l

strongly impact process performance

and equipment costs. A consensus and

final standardization of substrate size

and format will be required to finally

get panel-based packaging technology

widely adopt ed . A broad r a nge of

different substrate formats are currently

under investigation, i.e., 300×300mm,

370×470mm, 508×508mm, 510×515mm,

600×600mm, or even larger.

Be s i d e s p h o t o l i t h og r a p hy, Cu

deposition to create the RDL trace is a key

process step for fan-out packaging, both

on-wafer and on-panel. Key challenges,

latest technology developments, and test

results at the panel level will be presented

in the following sections.

Technology challenges for panel


Wit h t he t r a n sfe r of FOWLP t o

FOPLP, the industry strives to reduce

manufacturing costs. However, there are

some process challenges associated with

fan-out packaging in general that need to

be addressed also at the panel level.

During an electroplating process,

Cu material is typically deposited into