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Chip Scale Review March • April • 2018


Fan-out wafer- and panel-level technology for

advanced LED packaging

By Tanja Braun, Ruben Kahle, Stefan Raatz, Pascal Graap, Ole Hölck, Joerg Bauer, Karl-Friedrich Becker, Rolf Aschenbrenner

[Fraunhofer Institute for Reliability and Microintegration]

; Steve Voges, Marc Dreissigacker, Klaus-Dieter Lang


University Berlin, Microperipheric Center]

; Jürgen Moosburger, Frank Singer, Lutz Höppel

[OSRAM Opto Semiconductors GmbH]

an-out wafer-level packaging

( FOWLP) no t on ly h a s a

high potential for significant

package miniaturization with respect to

package volume, but also in thickness.

It can be used for multi-chip packages

f o r s y s t em- i n - p a c k a g e (S i P) a n d

heterogeneous integration. Heterogeneous

system integration includes also 3D

routing of electrical signals and double-

sided redistribution layers. Together with

the possibility of low thermal resistance,

FOWLP might also offer opportunities for

LED packaging.

Besides the development to higher

2D and 3D integration, a second trend

is the movement from wafer- to panel-

level for fan-out technologies, mainly

driven by lowering packaging cost.

Increasing the embedding substrate

size does not only mean an upscaling

of the existing technologies, but may

lead to a change f rom usi ng wafer

processing infrastructure to that used

for panels. This is especially true when

moving from round wafer sizes to larger

rectangular panel formats. Here also,

new materials and processes have to be

taken into account [1].

LED package concept

General lighting by the use of LED

chips is one of the strongly growing

ma r ke t s t o d ay, a nd l ow- c o s t a nd

large-area packaging is a demand [2].

Therefore, a blue LED with an area of



and a thickness of 120µm has

been chosen for package development.

The LED has one contact pad on the

topside and needs an additional electrical

connection to the backside. The overall

concept for the SMD-compatible single

LED package is shown in

Figure 1


The package size was designed to



allowing the integration

of a through-mold via (TMV) with a

100µm diameter routing the contact

from the topside to the surface mount

device-compatible (SMD) pads on the

backside. The backside of the LED is

connected by a blind via with a diameter

of 250µm. To enable subsequent blind

v i a ma nu f a c t u r i ng , i ncl ud i ng v i a

drilling through the mold and electrical

connection by plating, the LED was

prepared with 5µm Cu on the backside.

The backside via also strongly supports

the cooling of the LED. Here, larger

blind vias or multiple vias could even

further improve the thermal concept and

design of the package.

Process flow

For LED packaging, a “mold first”

face-down approach has been selected

as the light-emit ting surface of the

LED can be opened by the lithography

step in the redistribution layer (RDL).

The proposed packaging process f low

starts with face-down LED assembly

on an intermediate carrier followed by

overmolding using compression molding,

and debonding of the molded wafer/

panel from the carrier. The next step is

laser drilling of TMVs to route contacts

from front to backside, and blind vias to

access the backside of the LED. Before

application of the RDL, the vias have

to be cleaned of laser ablation residues.

A topside RDL is manufactured using

a photosensitive dielectric layer and

Cu plating base sputtering followed by

a plating step. The backside RDL is

applied by direct metallization on the

mold, also using sputtering and plating

steps. Whereas through-mold and blind-

via metallization is done by palladium

activation first, and then copper plating.

Cu structuring is done by etching for

conductor line and SMD pad forming.

Finally, a solder mask is applied on the

backside and package singulation is done

by laser or blade dicing. The schematic

process flow is summarized in

Figure 2


Package developmen t s a t t he

wafer level

The process developments and the

overall proof of concept for the LED fan-

out wafer/panel-level packaging approach

has been done on 200mm wafers. All

materials, equipment and processes have

been selected and evaluated for direct

upscaling to panel size. Wafer design has

been set up to reduce the number of dies

and assembly time. Therefore, package

density has been reduced without having


Figure 1:

Schematic LED fan-out wafer/panel-

level package.

Figure 2:

Process flow LED fan-out wafer/panel-

level packaging.