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Chip Scale Review March • April • 2018

[ChipScaleReview.com]

7

Localizing defects in 3D chips

Kristof J. P. Jacobs

imec

Technology

Trends

46

Industry News

CONTENTS

March • April 2018

Volume 22, Number 2

The photo is a graphical representation of

an intermediate step in the RDL-first fan-out

process whereby the dies are placed on top of the

redistribution layer (RDL) architecture before

overmolding. Prior steps in the process include

application of a release layer to the carrier,

followed by addition of redistribution layers on

top of the release layer. The RDL-first fan-out

process offers distinctive advantages in terms of

reduced known good die (KGD) loss, improved

line/space density, etc.

Cover photo courtesy of Brewer Science Inc.

DEPARTMENTS

FEATURE ARTICLES

10 Sacrificial laser release materials for RDL-first fan-out packaging Ramachandran K. Trichur, Rama Puligadda, Tony D. Flaim Brewer Science, Inc. 17 Extending plating performance to enable FOPLP Christian Ohde, Henning Hübner, Mustafa Özkök, Ralph Zoberbier, James Welsh Atotech Deutschland GmbH 31 HDAP connectivity verification: what you need to know Tarek Ramadan Mentor, a Siemens Business 37 Have you designed for manufacturing test? Gerard John Amkor Technology, Inc. 43 Flexible hybrid electronics: System as package Wilfried Bair NextFlex 26 Fan-out wafer- and panel-level technology for advanced LED packaging Tanja Braun, Ruben Kahle, Stefan Raatz, Pascal Graap, Ole Hölck, Joerg Bauer, Karl-Friedrich Becker, Rolf Aschenbrenner Fraunhofer Institute for Reliability and Microintegration ; Steve Voges, Marc Dreissigacker, Klaus-Dieter Lang Technical University Berlin, Microperipheric Center ; Jürgen Moosburger, Frank Singer, Lutz Höppel OSRAM Opto Semiconductors GmbH