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31

Chip Scale Review March • April • 2018

[ChipScaleReview.com]

By Tarek Ramadan

[Mentor, a Siemens Business]

HDAP connectivity verification: what you need to know

d v a n c e d i n t e g r a t e d

c i r c u i t ( IC ) p a c k a g i n g

ha s moved wel l beyond

t he expe r iment a l a nd p r ot ot y pi ng

stages [1]. Several leading foundries

a nd out sou r ced a s s embly a nd t e s t

(OSAT) companies now offer high-

density advanced packaging (HDAP)

services to their customers. The most

common approaches currently offered

by fou nd r ie s /OSATS a r e t he 2 .5D

IC (inter poser-based) style and fan-

out wafer-level packaging (FOWLP)

approach (single die or multi die), as

shown in

Figure 1

.

Because the interposer in a 2.5D IC

is similar to a traditional die (except

that it doesn’t include active devices),

IC design groups usually own the 2.5D

IC de sign , and use an IC- or ient ed

design (Manhattan shapes in the layout

database, SPICE/Verilog as the source

netlist, etc.) and physical verification

(design rule checking, or DRC) sign-off

approach. In a FOWLP package, package

design groups usually adopt design

techniques that use spreadsheets to

capture the design intent, and in-design

manufact u r i ng checks for physical

verification of the package construction.

Although the manufacturing steps and

owners for every HDAP technology can

be different (2.5D IC vs. FOWLP vs.

something else), and each technology

uses different data formats and tools, the

verification process is almost the same.

In both cases, however, the HDAP

verif ication f low t raditionally does

not include any automated layout vs.

schematic (LVS) sign-off. Automated

LVS is not historically popular in the

packaging world because the number

of components and required I/Os is

usually small, so a simple spreadsheet

or bonding diagram is sufficient for

an eyeball check. However, as HDAP

evolves and its use expands, the need

for an automated f low to detect and

highlight package connectivity errors

has become apparent.

Automated HDAP LVS

At the IC level, the LVS process

ensures that the physical layout creates

the elect r ical ci rcuits as designed.

Further electrical analysis and simulation

identifies such factors as parasitic effects,

reliability protection, predicted electrical

performance, etc.

For an HDAP design, the “LVS” process

focuses on verifying the connectivity

between all components in the HDAP. An

automated HDAP LVS flow in its simplest

form should verify that the interposer/

package GDSII correctly connects die-

to-die (for multi-die systems) and die-

to-C4/BGA bumps (for both single-die

and multi-die systems), as intended by the

designer. Checks that can be used to verify

connectivity through an entire assembly

stack should include (at a minimum) the

following types:

• Interposer/package standalone

- Identify texted shorts and opens

- Verify text labels vs. source

netlist pins

• Interposer/package + virtual die pins

- G e n e r a t e d i e p i n s ’ GD S

f rom subst rate connect ivit y

planning data

- Use virtual die pins to check

connectivity from die-to-BGA

through interposer/package

• Interposer/package full connectivity

- Source netlist = SPICE, Verilog,

or substrate connectivity

planning spreadsheet

- User-provided die GDS

- Use real die pins to check

connectivity from die-to-BGA

through interposer/package

Debugg ing connect iv it y errors.

Assuming that an automated HDAP LVS

f low is in use, it is still a challenge—

especially for the package designers—to

debug the resulting package connectivity

errors efficiently, particularly if the

number of highlighted errors is huge.

However, there are a few simple questions

designers can use to help simplify and

speed up the debugging process.

1. Do I have pin naming issues in

the source netlist vs. the layout?

This is a typical issue in which the

designer uses different pin naming

conventions in the system source

netlist vs. the interposer/package

layout (neither includes dummy

resistors). For example,

Figure 2

shows two connected pins that are

named A (die pin) and B (package

pin) in the source netlist. Those two

pins are represented by two bumps

in the layout: BUMP_A (die pin) and

BUMP_B (package pin). Although

BUMP_A and BUMP_B may be

connected correctly in the layout, an

HDAP LVS flow will not be able to

identify this as a correct connection

and errors will be f lagged, as the

names are different. When this issue

is present, the HDAP LVS f low

A

Figure 1:

The most common HDAP styles currently in use are the 2.5D IC and the FOWLP.

Figure 2:

Using different pin names in the source

netlist (left) and the layout (right) can make it

impossible for the HDAP LVS process to verify the

connectivity in the layout.