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Chip Scale Review March • April • 2018


By Gerard John

[Amkor Technology, Inc.]

Have you designed for manufacturing test?

urrent trends in chip design

p r omo t e t he conc e p t of

designed for test (DfT) and

designed for manufacturing (DfM). With

DfT, designers add scan chains and built-

in self-test (BIST) structures, etc., which

ease the job of test engineers in silicon

fault detection. On the other hand, DfM

puts in place rules that will enable very

quick ramps to high-volume production

with multiple designs in multiple fabs. As

noted by Intel’s Clair Webb in the Intel

Technology Journal, “The design and

process have to be manufacturable at the

beginning of the ramp. Design rules have to

be defined early in the process development

work to allow product design to be done in

parallel with the process development [1].”

Webb’s statements are commonplace

in the f ront end of the chip design

process (

Figure 1

), but do not guarantee

a design that is ready for manufacturing

test or high-volume test. For a chip

to be “designed for manufact u r i ng

test” (DfMT) early in the process, the

designer must consider the capabilities

and limitations of the manufacturing

test facility and design accordingly.

Furthermore, if the designed chip is

assembled and tested at an outsourced

semiconductor assembly and test (OSAT)

factor y, it is impor tant for the chip

designer to align with the OSAT mindset.

Th is a r t icle descr ibes t he OSAT

mindset, constraints, and capabilities

of the manufacturing test floor. It also

discusses several types of testing options

such as wafer sort, partially-assembled

test, final test, system-level test, and

examines how the test specifications and

the addition of test insert points can affect

the cost of the product.


In his book,

Processes and Design

for Manufacturing

[2], Sherif El Wakil

states, “Manufacturing can be defined

as the transformation of raw materials

into useful products using the easiest and

least expensive methods. It is not enough,

therefore to process some raw materials

and obtain the desired product. It is, in

fact, of major importance to achieve this

goal by employing the easiest, fastest and

most efficient methods. If less efficient

techniques are used, the production cost

of the manufactured part will be high,

and the part will not be as competitive

as similar par ts produced by other

manufacturers. Also, the production time

should be as short as possible to capture a

larger market share [2].”

Similarly, with manufacturing test, it

is not enough to classify parts as pass

or fail, but to achieve this goal in the

easiest, fastest and most efficient way.

A product is considered manufacturable

if it can be mass produced following

a recipe that produces products with

consistent performance, generating

little or no rejects, all within the time,

resource and cost budgets. With an

integrated circuit (IC), the ultimate

decider whether the device is production

ready is measured by its yield, while the

loss associated with materials, and labor

have a negligible impact on the viability

of the business case.

In the semiconductor industry, DfM

and Df T are hot topics with design

eng i nee r s real i z i ng t hei r st r at eg ic

impor t ance i n t he f ront end of t he

manufacturing process. However, when a

design/development engineer visualizes

the process of releasing a device to

manufacturing test, the mistaken picture

of manufacturing test as involving little

more than handing over test hardware,

software and accompanied by on-site

training comes to mind. Unfortunately,

this distorted view of manufacturing test

is created and fueled by the shallow and

qualitative way by which the subject of

manufacturing test is understood. Much of

this can be attributed to the secrecy under

which most test production floors operate

and thereby the limited knowledge of test

floor operations.

Manufacturing test refers to the process

when a device moves from new product

i nt roduct ion (NPI ) to h igh-volume

manufacturing (HVM), where tens of

thousands of parts are tested each day.

At HVM, the key elements that govern

the cost of testing are equipment cost and

time. While the cost for test equipment

(testers, probers and handlers) (see



) is fixed and better understood, the time

aspect is not. When considering DfMT,

one must consider the time that is taken to

set up the test cell (setup time), time taken

for the decision to be made whether the

device under test (DUT) is good or has

failed the test sequences (test time), the

time that is taken to retest a device, if the

initial data was inconclusive (retest time),

and the time taken for the device to be

moved from the input medium to the test

position (test socket or die location) and

then to the output medium (index time).

An IC that follows DfMT will allow

the use of the lowest cost tester and an

efficient material handler. The design

p r ov ide s a good ba l a nc e b e t we e n

multi-site operation (parallel test) and

tester resources (cost), low setup times

employing low-complexity test hardware

and sof twa re, as well as a hand ler

optimized for binning parts based on

the test results. Additionally, if the test

requirement calls for testing at other than

room temperatures, the design must be

robust enough that device performances

are not affected by rapid heating and

cooling methods employed by the handler

to reduce temperature transition times.


Figure 1:

Test equipment.