Chip Scale Review - March April 2020

8 Chip Scale Review March • April • 2020 [ChipScaleReview.com] interconnect level, we have developed materials and processes to minimize RC delays with lower resistance and lower capacitance redistribution layer (RDL) wiring. At the system level, it can be directly assembled to both Si ICs and organic boards, without another layer of packaging—unlike with Si packages. A number of new packaging paradigms developed in the Georgia Tech consortium include large-panel processing (in excess of 500mm sizes), development of 1-micron lithography tools, low dielectric constant polymer dielectric materials and processes with a high aspect ratio of conductors with lower resistance and a high degree of planarity without chemical mechanical polishing (CMP), and barrier metals to improve electromigration of closely- spaced conductors. In addition, a new 3D pa ckage a r ch it e c t u r e, r efe r r ed to as 3DGPE, that advances 3D by embedding with ultra-short and low-RC interconnections, helps achieve higher bandwidth than with Si interposers. Optoelectronic packaging Photonics has long been viewed as providing higher bandwidth at lower power in smaller and lighter packages than electronics. It is also immune to electromagnetic interference (EMI). The technology has been used not only for long- dist ance commun icat ions, b u t a l s o f o r s y s t em s t o s y s t em s i n t e r c o n n e c t i o n s . As e l e c t r o n i c s reach bandwidth limits on account of Moore’s Law limits as described above, optoelectronics becomes a necessary solution to achieve bandwidths towards 1Pb/s. Within optoelectronics, there are many ways to improve bandwidth including multiplexing: more links per optical channel, wavelength-division multiplexing (i.e., an approach that uses multiple wavelengths over the same medium), as well as modulation methods, such as pulse amplitude modulation—an approach that provides more bits in the same amount of time. While there are many ways to fabricate optoelect ron ics modu les, t he most desirable technology is one that is made of silicon, as silicon is the most studied and used in microelectronics. This is referred to as Si photonics, whereby electronic and photonic devices are integrated onto one single silicon chip using CMOS fabrication techniques. While there are many advantages to this technology, including smaller size (400nm waveguide width) and mature CMOS manufacturing processes, it also has many challenges that include fiber coupling and the fact that Si doesn’t lase, requiring alternate on-silicon light sources. Quantum electronics Quantum physics has been a branch of physics for decades with many branches of study within it that include quantum chemistry, quantum simulations, quantum machine learning, quantum algorithms, and quantum communications. Quantum computing (QC) has been a topic of research for more than two decades. As Moore’s Law-driven electronics begins to slow down in terms of its ability to provide increased computing at lower power, scientists at companies like IBM began to explore quant um devices. Unlike current digital systems that are programmed with bits as data units, either 0 or 1, quantum computers use qubits, which can represent a combination of both 0 and 1 at the same time, based on the principle of superposition.This difference makes quantum computers expone n t i a l ly f a s t e r t h a n cu r r e n t mainframes and servers. In addition, quantum computers can do multiple calculations with multiple inputs simultaneously, unlike today’s computers that can handle only one set of inputs and one calculation at a time. With 50 qubits, for example, the computing power can be 2 to the power of 50. When the industry gets to 1000 qubits that becomes 2 to the power of 1000. Currently, qubits are at about 50, but even at these low numbers, the computing power has been demonstrated well in excess of the best supercomputers at much lower power. Two factors driving qubits are quality and number. Currently, the most visible and dominant companies include IBM, Microsoft, and Google. All the large semiconductor and systems companies are known to have large internal programs [6]. Applications for quantum computing are many and include: 1) Rapid R&D for chemicals and pharmaceutical materials with simulations; 2) Supercomputing power for autonomous vehicles with quantum AI to reduce fatalities to zero; and 3) Eliminating cybersecurity issues. Quant um computers are expected to be developed in a Moore’s law–like fashion—every year from 50 today, to about 5-10,000 by 2030. Amazon Web Services, Microsoft Azure, IBM, and others have already announced quantum offerings. Initially, quantum computing adoption will be a hybrid approach, in which parts of the problem would be handled by classical computing, and other parts by quantum AI. Mimicking the human brain may be the ultimate AI. References 1. R. Keys, “Physical limits of silicon transistors and circuits,” Rep. prog. physics, 68, 2701-2746, 2005. 2. G. E. Moore, “Crammi ng more components into integrated circuits,” Electronics, 38(8), 1965. 3. R. H. Dennard, IEEE J. Solid State Circuits, SC-9, 256, 1974. 4. P. Ruch , e t a l., “Towa r d f ive - dimensional scaling: How density imp r ove s ef f ic ie ncy i n f u t u r e computers,” IBM J. R&D Vol. 55(5) 151-157, 2011. 5. H. Moravec, “When will computer h a r d w a r e m a t c h t h e h u m a n brain,” J. Evol. Technology, online transhumanist.com/Moravec.htm 6. Alexandre Ménard, I. Ostojic, M. Patel, D. Volz, “A game plan for quantum computing,” McKinsey Quarterly, Feb. 2020. Biography Rao Tummala is a Distinguished and Endowed Chair Professor Emeritus at Georgia Tech, USA. Prior to Georgia Tech, he was an IBM Fellow. He has published about 800 technical papers and invented technologies that resulted in 100 patents. He has written seven books including the first modern Handbook in packaging, Microelectronics Packaging Handbook (1988), and the latest undergrad textbook, Fundamentals of Device and Systems Packaging (2019). He was a past President of IEEE EPS and IMAPS and is an IEEE Fellow and member of the National Academy of Engineering. Email rao.tummala@ece.gatech.edu

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